Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bit…

…s swapped)

Change-Id: I8200ca88f315521bb8e24bb1f6d85f30fe6d9841
Original-Change-Id: If02e5e31c768c62bbdf37c15b5146bacaaf38d80
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36173
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55467
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -2303,6 +2303,25 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the
+      DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum.
+      Post DD2.** will have a hardware enabled fix for this (HW389360).
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -2354,6 +2373,7 @@
       </chip>
     </chipEcFeature>
   </attribute>
+
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   <!-- End Memory Section                                                   -->
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