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Add unmasks for REG1 and REG2 versions of OMI_FIR for Axone
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Change-Id: I1ff1255415b2a67a91520b7c12a68104995815b9
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/94060
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/94115
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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@stermole @dcrowell77
stermole authored and dcrowell77 committed Apr 2, 2020
1 parent 875d8fc commit e9687ad
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Showing 3 changed files with 107 additions and 6 deletions.
14 changes: 14 additions & 0 deletions src/import/chips/p9/common/include/p9a_mc_scom_addresses_fixes.H
View file
Expand Up @@ -58,4 +58,18 @@ static const uint64_t P9A_MC_REG0_OMI_FIR_ACTION1 = 0x
static const uint64_t P9A_MC_REG0_OMI_FIR_MASK_AND = 0x07013344ull;
static const uint64_t P9A_MC_REG0_OMI_FIR_MASK_OR = 0x07013345ull;

static const uint64_t P9A_MC_REG1_OMI_FIR = 0x07013380ull;
static const uint64_t P9A_MC_REG1_OMI_FIR_MASK = 0x07013383ull;
static const uint64_t P9A_MC_REG1_OMI_FIR_ACTION0 = 0x07013386ull;
static const uint64_t P9A_MC_REG1_OMI_FIR_ACTION1 = 0x07013387ull;
static const uint64_t P9A_MC_REG1_OMI_FIR_MASK_AND = 0x07013384ull;
static const uint64_t P9A_MC_REG1_OMI_FIR_MASK_OR = 0x07013385ull;

static const uint64_t P9A_MC_REG2_OMI_FIR = 0x070133C0ull;
static const uint64_t P9A_MC_REG2_OMI_FIR_MASK = 0x070133C3ull;
static const uint64_t P9A_MC_REG2_OMI_FIR_ACTION0 = 0x070133C6ull;
static const uint64_t P9A_MC_REG2_OMI_FIR_ACTION1 = 0x070133C7ull;
static const uint64_t P9A_MC_REG2_OMI_FIR_MASK_AND = 0x070133C4ull;
static const uint64_t P9A_MC_REG2_OMI_FIR_MASK_OR = 0x070133C5ull;

#endif
63 changes: 58 additions & 5 deletions src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H
View file
Expand Up @@ -291,15 +291,21 @@ inline fapi2::ReturnCode after_p9a_chiplet_scominit(const fapi2::Target<fapi2::T
fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc3 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc4 = fapi2::FAPI2_RC_SUCCESS;
fapi2::ReturnCode l_rc5 = fapi2::FAPI2_RC_SUCCESS;

// Create registers and check success
mss::fir::reg<P9A_MC_LOCAL_FIR> l_mc_local_fir_reg(i_target, l_rc1);
mss::fir::reg<P9A_MC_MCBISTFIRQ> l_mc_mcbistfirq_reg(i_target, l_rc2);
mss::fir::reg<P9A_MC_REG0_OMI_FIR> l_mc_omi_fir_reg(i_target, l_rc3);
mss::fir::reg<P9A_MC_REG0_OMI_FIR> l_mc_reg0_omi_fir_reg(i_target, l_rc3);
mss::fir::reg<P9A_MC_REG1_OMI_FIR> l_mc_reg1_omi_fir_reg(i_target, l_rc4);
mss::fir::reg<P9A_MC_REG2_OMI_FIR> l_mc_reg2_omi_fir_reg(i_target, l_rc5);

FAPI_TRY(l_rc1, "unable to create fir::reg for P9A_MC_LOCAL_FIR 0x%08X", P9A_MC_LOCAL_FIR);
FAPI_TRY(l_rc2, "unable to create fir::reg for P9A_MC_MCBISTFIRQ 0x%08X", P9A_MC_MCBISTFIRQ);
FAPI_TRY(l_rc3, "unable to create fir::reg for P9A_MC_REG0_OMI_FIR 0x%08X", P9A_MC_REG0_OMI_FIR);
FAPI_TRY(l_rc4, "unable to create fir::reg for P9A_MC_REG1_OMI_FIR 0x%08X", P9A_MC_REG1_OMI_FIR);
FAPI_TRY(l_rc5, "unable to create fir::reg for P9A_MC_REG2_OMI_FIR 0x%08X", P9A_MC_REG2_OMI_FIR);

// Write LOCAL_FIR register per Axone unmask spec
FAPI_TRY(l_mc_local_fir_reg.recoverable_error<P9A_MC_LOCAL_FIR_IN0>()
Expand All @@ -322,30 +328,75 @@ inline fapi2::ReturnCode after_p9a_chiplet_scominit(const fapi2::Target<fapi2::T
switch(l_pos)
{
case 0:
l_mc_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();

l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();

l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();

break;

case 1:
l_mc_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();

l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();

l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();

break;

case 2:
l_mc_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();

l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();

l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();

break;

default:
Expand Down Expand Up @@ -389,7 +440,9 @@ inline fapi2::ReturnCode after_p9a_chiplet_scominit(const fapi2::Target<fapi2::T
}

// Write MC_OMI_FIR register now that it's been set up in the loop above
FAPI_TRY(l_mc_omi_fir_reg.write());
FAPI_TRY(l_mc_reg0_omi_fir_reg.write());
FAPI_TRY(l_mc_reg1_omi_fir_reg.write());
FAPI_TRY(l_mc_reg2_omi_fir_reg.write());

for (const auto& l_mcc : mss::find_targets<fapi2::TARGET_TYPE_MCC>(i_target))
{
Expand Down
36 changes: 35 additions & 1 deletion src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir_traits.H
View file
Expand Up @@ -82,7 +82,7 @@ struct firTraits<P9A_MCC_USTLFIR>
};

///
/// @brief FIR Register Traits for base MC_OMI_FIR_REG
/// @brief FIR Register Traits for base MC_REG0_OMI_FIR_REG
///
template <>
struct firTraits<P9A_MC_REG0_OMI_FIR>
Expand All @@ -98,6 +98,40 @@ struct firTraits<P9A_MC_REG0_OMI_FIR>
static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_MC;
};

///
/// @brief FIR Register Traits for base MC_REG1_OMI_FIR_REG
///
template <>
struct firTraits<P9A_MC_REG1_OMI_FIR>
{
static constexpr uint64_t REG = P9A_MC_REG1_OMI_FIR;
static constexpr uint64_t ACT0 = P9A_MC_REG1_OMI_FIR_ACTION0;
static constexpr uint64_t ACT1 = P9A_MC_REG1_OMI_FIR_ACTION1;
static constexpr uint64_t MASK = P9A_MC_REG1_OMI_FIR_MASK;
static constexpr uint64_t MASK_AND = P9A_MC_REG1_OMI_FIR_MASK_AND;
static constexpr uint64_t MASK_OR = P9A_MC_REG1_OMI_FIR_MASK_OR;

// Target type of this register
static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_MC;
};

///
/// @brief FIR Register Traits for base MC_REG2_OMI_FIR_REG
///
template <>
struct firTraits<P9A_MC_REG2_OMI_FIR>
{
static constexpr uint64_t REG = P9A_MC_REG2_OMI_FIR;
static constexpr uint64_t ACT0 = P9A_MC_REG2_OMI_FIR_ACTION0;
static constexpr uint64_t ACT1 = P9A_MC_REG2_OMI_FIR_ACTION1;
static constexpr uint64_t MASK = P9A_MC_REG2_OMI_FIR_MASK;
static constexpr uint64_t MASK_AND = P9A_MC_REG2_OMI_FIR_MASK_AND;
static constexpr uint64_t MASK_OR = P9A_MC_REG2_OMI_FIR_MASK_OR;

// Target type of this register
static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_MC;
};

///
/// @brief FIR Register Traits for base MC_LOCAL_FIR
///
Expand Down

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