Skip to content

Commit

Permalink
Fix DL_OMI_FIR unmasks after p9_chiplet_scominit to be DL specific
Browse files Browse the repository at this point in the history 
Change-Id: I5fdfeaa6d407702c649023efd134aadcde04200a
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/94976
Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: ANDRE A MARIN <aamarin@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/94996
Reviewed-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M Crowell <dcrowell@us.ibm.com>
  • Loading branch information
@stermole @dcrowell77
stermole authored and dcrowell77 committed Apr 14, 2020
1 parent 85992ee commit eed98f1
Show file tree
Hide file tree
Showing 2 changed files with 155 additions and 86 deletions.
230 changes: 144 additions & 86 deletions src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H
View file
Expand Up @@ -320,92 +320,150 @@ inline fapi2::ReturnCode after_p9a_chiplet_scominit(const fapi2::Target<fapi2::T

for (const auto& l_omic : mss::find_targets<fapi2::TARGET_TYPE_OMIC>(i_target))
{
const auto l_pos = mss::relative_pos<fapi2::TARGET_TYPE_MC>(l_omic);

// Set up MC_OMI_FIR register per Axone unmask spec
// Note that there are child-target-specific FIR bits in this reg, so we need to check
// what's configured inside the OMIC loop
switch(l_pos)
for (const auto& l_omi : mss::find_targets<fapi2::TARGET_TYPE_OMI>(l_omic))
{
case 0:
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();

l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();

l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();

break;

case 1:
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();

l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();

l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();

break;

case 2:
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();

l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();

l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();

break;

default:
FAPI_ASSERT(false,
fapi2::MSS_INVALID_OMIC_POSITION().
set_POSITION(l_pos).
set_OMIC_TARGET(l_omic),
"Invalid OMIC position (%d) for %s", l_pos, mss::c_str(l_omic));
break;
// Set up MC_OMI_FIR register per Axone unmask spec
// Note that there are child-target-specific FIR bits in these regs, so we need to check
// what's configured and unmask the corresponding group of FIRs in the right reg
// OMIC relative pos ==> REG0/1/2
// OMI relative pos ==> DL0/1/2
const auto l_omic_pos = mss::relative_pos<fapi2::TARGET_TYPE_MC>(l_omic);
uint8_t l_omi_pos = 0;
FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_OMI_DL_GROUP_POS, l_omi, l_omi_pos) );

switch(l_omic_pos)
{
case 0:
switch(l_omi_pos)
{
case 0:
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();
break;

case 1:
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();
break;

case 2:
l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();
break;

default:
FAPI_ASSERT(false,
fapi2::MSS_INVALID_OMI_POSITION().
set_POSITION(l_omi_pos).
set_OMI_TARGET(l_omi),
"Invalid OMI position (%d) for %s", l_omi_pos, mss::c_str(l_omi));
break;
}

break;

case 1:
switch(l_omi_pos)
{
case 0:
l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();
break;

case 1:
l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();
break;

case 2:
l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();
break;

default:
FAPI_ASSERT(false,
fapi2::MSS_INVALID_OMI_POSITION().
set_POSITION(l_omi_pos).
set_OMI_TARGET(l_omi),
"Invalid OMI position (%d) for %s", l_omi_pos, mss::c_str(l_omi));
break;
}

break;

case 2:
switch(l_omi_pos)
{
case 0:
l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN>();
break;

case 1:
l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN>();
break;

case 2:
l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FATAL_ERROR>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_DATA_UE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_X4_MODE>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_TIMEOUT>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN>()
.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN>();
break;

default:
FAPI_ASSERT(false,
fapi2::MSS_INVALID_OMI_POSITION().
set_POSITION(l_omi_pos).
set_OMI_TARGET(l_omi),
"Invalid OMI position (%d) for %s", l_omi_pos, mss::c_str(l_omi));
break;
}

break;

default:
FAPI_ASSERT(false,
fapi2::MSS_INVALID_OMIC_POSITION().
set_POSITION(l_omic_pos).
set_OMIC_TARGET(l_omic),
"Invalid OMIC position (%d) for %s", l_omic_pos, mss::c_str(l_omic));
break;
}
}

fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS;
Expand Down Expand Up @@ -439,7 +497,7 @@ inline fapi2::ReturnCode after_p9a_chiplet_scominit(const fapi2::Target<fapi2::T
.write()) );
}

// Write MC_OMI_FIR register now that it's been set up in the loop above
// Write MC_OMI_FIR registers now that they've been set up in the loop above
FAPI_TRY(l_mc_reg0_omi_fir_reg.write());
FAPI_TRY(l_mc_reg1_omi_fir_reg.write());
FAPI_TRY(l_mc_reg2_omi_fir_reg.write());
Expand Down
11 changes: 11 additions & 0 deletions src/import/generic/procedures/xml/error_info/generic_error.xml
View file
Expand Up @@ -1292,6 +1292,17 @@
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_INVALID_OMI_POSITION</rc>
<description> An invalid OMI position was found in FIR unmask function</description>
<ffdc>POSITION</ffdc>
<ffdc>OMI_TARGET</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
</hwpError>

<hwpError>
<rc>RC_MSS_PLUG_RULES_SINGLE_DDIMM_IN_WRONG_SLOT</rc>
<description>
Expand Down

0 comments on commit eed98f1

Please sign in to comment.