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Setup INTP bars correctly when memory is swapped on master proc
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In the event that no memory is detected behind proc0. We will attempt
to use the memory behind a slave proc instead. When this occurs we
must adjust the interrupt bars to account for this swap

Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2
RTC: 173527
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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@crgeddes @wghoffa
crgeddes authored and wghoffa committed Jun 2, 2017
1 parent f7f718f commit f3dd0b0
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Showing 5 changed files with 93 additions and 37 deletions.
5 changes: 5 additions & 0 deletions src/include/arch/memorymap.H
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Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,11 @@ inline uint64_t computeMemoryMapOffset( uint64_t i_baseAddr,
*/
constexpr uint64_t MMIO_GROUP0_CHIP0_XSCOM_BASE_ADDR = 0x000603FC00000000;
constexpr uint64_t MMIO_GROUP0_CHIP0_LPC_BASE_ADDR = 0x0006030000000000;
constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR = 0x0006030203000000;
constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR = 0x0006030203100000;
constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR = 0x0006020000000000;
constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR = 0x00060302031C0000;
constexpr uint64_t MMIO_GROUP0_CHIP0_INTP_BASE_ADDR = 0x0003FFFF80000000;


#endif //#ifndef _MEMORYMAP_H
25 changes: 0 additions & 25 deletions src/usr/targeting/common/genHwsvMrwXml.pl
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Original file line number Diff line number Diff line change
Expand Up @@ -3884,7 +3884,6 @@ sub generate_proc

# Calculate the FSP and PSI BRIGDE BASE ADDR
my $fspBase = 0;
my $psiBase = 0;
foreach my $i (@{$psiBus->{'psi-bus'}})
{
if (($i->{'processor'}->{target}->{position} eq $proc) &&
Expand All @@ -3893,9 +3892,6 @@ sub generate_proc
#FSP MMIO address
$fspBase = 0x0006030100000000 + $nodeSize*$lognode +
$chipSize*$logid;
#PSI Link address
$psiBase = 0x0006030203000000 + $nodeSize*$lognode +
$chipSize*$logid;
last;
}
}
Expand All @@ -3905,10 +3901,6 @@ sub generate_proc
printf( " <default>0x%016X</default>\n", $fspBase );
printf( " </attribute>\n" );

# PSI Link address
printf( " <attribute><id>PSI_BRIDGE_BASE_ADDR</id>\n" );
printf( " <default>0x%016X</default>\n", $psiBase );
printf( " </attribute>\n" );

#VAS Hypervisor Window Contexts address
printf( " <attribute><id>VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR</id>\n" );
Expand Down Expand Up @@ -3946,23 +3938,6 @@ sub generate_proc
0x0006030201400000 + $nodeSize*$lognode + $chipSize*$logid );
printf( " </attribute>\n" );

#XIVE - Controller Bar address
printf( " <attribute><id>XIVE_CONTROLLER_BAR_ADDR</id>\n" );
printf( " <default>0x%016X</default>\n",
0x0006030203100000 + $nodeSize*$lognode + $chipSize*$logid );
printf( " </attribute>\n" );

#XIVE - Thread Management Bar Address register 1
printf( " <attribute><id>XIVE_THREAD_MGMT1_BAR_ADDR</id>\n" );
printf( " <default>0x%016X</default>\n",
0x0006020000000000 + $nodeSize*$lognode + $chipSize*$logid );
printf( " </attribute>\n" );

#PSI HB - ESP space address
printf( " <attribute><id>PSI_HB_ESB_ADDR</id>\n" );
printf( " <default>0x%016X</default>\n",
0x00060302031C0000 + $nodeSize*$lognode + $chipSize*$logid );
printf( " </attribute>\n" );

#NX - RNG space address
printf( " <attribute><id>NX_RNG_ADDR</id>\n" );
Expand Down
16 changes: 12 additions & 4 deletions src/usr/targeting/common/processMrw.pl
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Original file line number Diff line number Diff line change
Expand Up @@ -750,16 +750,12 @@ sub setupBars
$targetObj->{TOPOLOGY}->{$group}->{$proc}++;

my @bars=( "FSP_BASE_ADDR",
"PSI_BRIDGE_BASE_ADDR",
"INTP_BASE_ADDR",
"VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR",
"VAS_USER_WINDOW_CONTEXT_ADDR",
"NVIDIA_NPU_PRIVILEGED_ADDR",
"NVIDIA_NPU_USER_REG_ADDR",
"NVIDIA_PHY0_REG_ADDR",
"NVIDIA_PHY1_REG_ADDR",
"PSI_HB_ESB_ADDR",
"XIVE_CONTROLLER_BAR_ADDR",
"NX_RNG_ADDR");

# Attribute only valid in naples-based systems
Expand All @@ -774,6 +770,18 @@ sub setupBars
if (!$targetObj->isBadAttribute($target,"XSCOM_BASE_ADDRESS") ) {
push(@bars,"XSCOM_BASE_ADDRESS");
}
if (!$targetObj->isBadAttribute($target,"PSI_BRIDGE_BASE_ADDR") ) {
push(@bars,"PSI_BRIDGE_BASE_ADDR");
}
if (!$targetObj->isBadAttribute($target,"INTP_BASE_ADDR") ) {
push(@bars,"INTP_BASE_ADDR");
}
if (!$targetObj->isBadAttribute($target,"PSI_HB_ESB_ADDR") ) {
push(@bars,"PSI_HB_ESB_ADDR");
}
if (!$targetObj->isBadAttribute($target,"XIVE_CONTROLLER_BAR_ADDR") ) {
push(@bars,"XIVE_CONTROLLER_BAR_ADDR");
}

foreach my $bar (@bars)
{
Expand Down
17 changes: 9 additions & 8 deletions src/usr/targeting/common/xmltohb/attribute_types.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -3579,8 +3579,9 @@
<default>0xFFFFFFFFFFFFFFFF</default>
</uint64_t>
</simpleType>
<persistency>non-volatile</persistency>
<persistency>volatile-zeroed</persistency>
<readable/>
<writeable/>
<hwpfToHbAttrMap>
<id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id>
<macro>DIRECT</macro>
Expand All @@ -3597,12 +3598,9 @@
<default>0xFFFFFFFFFFFFFFFF</default>
</uint64_t>
</simpleType>
<persistency>non-volatile</persistency>
<persistency>volatile-zeroed</persistency>
<readable/>
<hwpfToHbAttrMap>
<id>ATTR_PROC_INTP_BAR_BASE_ADDR</id>
<macro>DIRECT</macro>
</hwpfToHbAttrMap>
<writeable/>
</attribute>

<attribute>
Expand Down Expand Up @@ -18959,8 +18957,9 @@ Measured in GB</description>
<simpleType>
<uint64_t></uint64_t>
</simpleType>
<persistency>non-volatile</persistency>
<persistency>volatile-zeroed</persistency>
<readable/>
<writeable/>
</attribute>

<attribute>
Expand All @@ -18971,8 +18970,9 @@ Measured in GB</description>
<simpleType>
<uint64_t></uint64_t>
</simpleType>
<persistency>non-volatile</persistency>
<persistency>volatile-zeroed</persistency>
<readable/>
<writeable/>
</attribute>


Expand All @@ -18985,6 +18985,7 @@ Measured in GB</description>
</simpleType>
<persistency>non-volatile</persistency>
<readable/>
<writeable/>
</attribute>

<attribute>
Expand Down
67 changes: 67 additions & 0 deletions src/usr/targeting/targetservicestart.C
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Original file line number Diff line number Diff line change
Expand Up @@ -497,6 +497,63 @@ static void adjustMemoryMap( TargetService& i_targetService )
TARG_ASSERT(false,"Mismatch between LPC and XSCOM BARs");
}

//Setup Interrupt Related Bars
ATTR_PSI_BRIDGE_BASE_ADDR_type l_psiBridgeBAR =
computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR,
l_groupId,
l_chipId);
TARG_INF( " PSI_BRIDGE_BAR =%.16llX", l_psiBridgeBAR );
l_procChip->setAttr<ATTR_PSI_BRIDGE_BASE_ADDR>(l_psiBridgeBAR);
if( l_swapVictim == l_procChip)
{
l_swapAttrs[ATTR_PSI_BRIDGE_BASE_ADDR] = l_psiBridgeBAR;
}

ATTR_XIVE_CONTROLLER_BAR_ADDR_type l_xiveCtrlBAR =
computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR,
l_groupId,
l_chipId);
TARG_INF( " XIVE_CONTROLLER_BAR =%.16llX", l_xiveCtrlBAR );
l_procChip->setAttr<ATTR_XIVE_CONTROLLER_BAR_ADDR>(l_xiveCtrlBAR);
if( l_swapVictim == l_procChip)
{
l_swapAttrs[ATTR_XIVE_CONTROLLER_BAR_ADDR] = l_xiveCtrlBAR;
}

ATTR_XIVE_THREAD_MGMT1_BAR_ADDR_type l_xiveThreadMgmtBAR =
computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR,
l_groupId,
l_chipId);
TARG_INF( " XIVE_THREAD_MGMT1_BAR =%.16llX", l_xiveThreadMgmtBAR );
l_procChip->setAttr<ATTR_XIVE_THREAD_MGMT1_BAR_ADDR>(l_xiveThreadMgmtBAR);
if( l_swapVictim == l_procChip)
{
l_swapAttrs[ATTR_XIVE_THREAD_MGMT1_BAR_ADDR] = l_xiveThreadMgmtBAR;
}

ATTR_PSI_HB_ESB_ADDR_type l_psiHbEsbBAR =
computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR,
l_groupId,
l_chipId);
TARG_INF( " PSI_HB_ESB_BAR =%.16llX", l_psiHbEsbBAR );
l_procChip->setAttr<ATTR_PSI_HB_ESB_ADDR>(l_psiHbEsbBAR);
if( l_swapVictim == l_procChip)
{
l_swapAttrs[ATTR_PSI_HB_ESB_ADDR] = l_psiHbEsbBAR;
}

ATTR_INTP_BASE_ADDR_type l_intpBAR =
computeMemoryMapOffset(MMIO_GROUP0_CHIP0_INTP_BASE_ADDR,
l_groupId,
l_chipId);
TARG_INF( " INTP_BAR =%.16llX", l_intpBAR );
l_procChip->setAttr<ATTR_INTP_BASE_ADDR>(l_intpBAR);
if( l_swapVictim == l_procChip)
{
l_swapAttrs[ATTR_INTP_BASE_ADDR] = l_intpBAR;
}
//finished setting up interrupt bars

// Set the rest of the BARs...
}

Expand All @@ -515,6 +572,16 @@ static void adjustMemoryMap( TargetService& i_targetService )
l_swapVictim, l_swapAttrs );
SWAP_ATTRIBUTE( ATTR_LPC_BUS_ADDR, l_pMasterProcChip,
l_swapVictim, l_swapAttrs );
SWAP_ATTRIBUTE( ATTR_PSI_BRIDGE_BASE_ADDR, l_pMasterProcChip,
l_swapVictim, l_swapAttrs );
SWAP_ATTRIBUTE( ATTR_XIVE_CONTROLLER_BAR_ADDR, l_pMasterProcChip,
l_swapVictim, l_swapAttrs );
SWAP_ATTRIBUTE( ATTR_XIVE_THREAD_MGMT1_BAR_ADDR, l_pMasterProcChip,
l_swapVictim, l_swapAttrs );
SWAP_ATTRIBUTE( ATTR_PSI_HB_ESB_ADDR, l_pMasterProcChip,
l_swapVictim, l_swapAttrs );
SWAP_ATTRIBUTE( ATTR_INTP_BASE_ADDR, l_pMasterProcChip,
l_swapVictim, l_swapAttrs );
// Handle the rest of the BARs...
}

Expand Down

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