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Add address translation (xlate) support for 4Gbx8 and unit tests
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Change-Id: I2539fa5237fcae61d334362e54325368c9b12a2a
CQ:SW415468
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52442
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52457
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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@aamarin @dcrowell77
aamarin authored and dcrowell77 committed Feb 19, 2018
1 parent 8d28433 commit f595ecf
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Showing 7 changed files with 945 additions and 202 deletions.
401 changes: 396 additions & 5 deletions src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
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247 changes: 246 additions & 1 deletion src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -113,6 +113,7 @@ class rowTraits<ROW15>
public:
static constexpr uint64_t ROW = 15;
static constexpr uint64_t MAX_MAP_VALUE = PORT_ADDRESS_7;
static constexpr uint64_t CLEAR_MAP = PORT_ADDRESS_0;

enum
{
Expand All @@ -132,6 +133,7 @@ class rowTraits<ROW16>
public:
static constexpr uint64_t ROW = 16;
static constexpr uint64_t MAX_MAP_VALUE = PORT_ADDRESS_7;
static constexpr uint64_t CLEAR_MAP = PORT_ADDRESS_0;

enum
{
Expand All @@ -151,6 +153,7 @@ class rowTraits<ROW17>
public:
static constexpr uint64_t ROW = 17;
static constexpr uint64_t MAX_MAP_VALUE = PORT_ADDRESS_7;
static constexpr uint64_t CLEAR_MAP = PORT_ADDRESS_0;

enum
{
Expand Down Expand Up @@ -196,6 +199,32 @@ fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief CLear row bits on the xlate register
/// @tparam T row enumerations to represent xlate master row bits
/// @tparam TT traits type defaults to rowTraits<T>
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @return FAPI2_RC_SUCCESS iff okay
///
template< rows T, typename TT = rowTraits<T> >
inline fapi2::ReturnCode clear_xlate_row( const uint64_t i_offset,
fapi2::buffer<uint64_t>& io_xlate0 )
{
FAPI_TRY( io_xlate0.clearBit( TT::SLOT0_ROW_VALID + i_offset ) );
io_xlate0.insertFromRight<TT::ROW_BIT_MAP, TT::ROW_BIT_MAP_LEN>(TT::CLEAR_MAP);

FAPI_DBG( "Set MCP0XLT0_SLOT%d_ROW%d_VALID at bit %d. "
"Set bits for MCP0XLT0_R%d_BIT_MAP with 0x%lx (start: %d, len: %d). "
"MCP0XLT0: 0x%016lx.",
(i_offset == 0 ? 0 : 1), TT::ROW, TT::SLOT0_ROW_VALID + i_offset, TT::ROW,
TT::CLEAR_MAP, TT::ROW_BIT_MAP, TT::ROW_BIT_MAP_LEN,
uint64_t(io_xlate0) );

fapi_try_exit:
return fapi2::current_err;
}

///
/// @class mrankTraits
/// @brief a collection of traits associated with the master rank xlate registers
Expand Down Expand Up @@ -1334,6 +1363,222 @@ fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind& i_kind,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 1R 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 1R 2H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 2R 8H 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );

///
/// @brief Perform initializations of the MC translation
/// @param[in] i_kind the DIMM to map
/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1
/// @param[in] i_largest whether or not we're the largest DIMM on the port.
/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify
/// @param[in,out] io_xlate2 a buffer representing the xlate register to modify
/// @note Called for 4R 4Gbx8 DDR4 RDIMM
/// @return FAPI2_RC_SUCCESS iff okay
///
fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind& i_kind,
const uint64_t i_offset,
const bool i_largest,
fapi2::buffer<uint64_t>& io_xlate0,
fapi2::buffer<uint64_t>& io_xlate1,
fapi2::buffer<uint64_t>& io_xlate2 );
} // ns mc
} // ns mss

Expand Down
22 changes: 22 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
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Original file line number Diff line number Diff line change
Expand Up @@ -21534,6 +21534,28 @@ fapi_try_exit:
return fapi2::current_err;
}

///
/// @brief ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW getter
/// @param[out] uint8_t& reference to store the value
/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
/// @note Switch that allows unsupported raw card references by providing a default raw
/// card
/// setting.
///
inline fapi2::ReturnCode mrw_allow_unsupported_rcw(uint8_t& o_value)
{

FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
o_value) );
return fapi2::current_err;

fapi_try_exit:
FAPI_ERR("failed accessing ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW: 0x%lx (system target)",
uint64_t(fapi2::current_err));
return fapi2::current_err;
}


///
/// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT getter
Expand Down

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