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Adds LRDIMM MWD coarse training step
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Change-Id: Ie8317b5a4542cf9a71f85d357cc2071b687d3cda
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68466
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Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68720
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Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
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Li Meng authored and crgeddes committed Dec 13, 2018
1 parent bd720a4 commit f7cb4b2
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Showing 4 changed files with 50 additions and 85 deletions.
37 changes: 37 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
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Original file line number Diff line number Diff line change
Expand Up @@ -398,6 +398,43 @@ static void mrs_rcd_helper( fapi2::buffer<uint64_t>& i_arr0 )
.template clearBit<TT::ARR0_DDR_ADDRESS_14>();
}

///
/// @brief Setup activate command instruction
/// @tparam T the target type of the chiplet which executes the CCS instruction
/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction
/// @param[in] i_target the DIMM this instruction is headed for
/// @param[in] i_rank the rank on this dimm
///
template< fapi2::TargetType T, typename TT = ccsTraits<T> >
inline instruction_t<T> act_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
const uint64_t i_rank)
{
fapi2::buffer<uint64_t> l_boilerplate_arr0;
fapi2::buffer<uint64_t> l_boilerplate_arr1;

// Set all CKE to high
l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH);

// ACT is high
l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ACTN>();

// RAS low, CAS low, WE low
l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_16>()
.template clearBit<TT::ARR0_DDR_ADDRESS_15>()
.template clearBit<TT::ARR0_DDR_ADDRESS_14>();

// Just leaving the row addresses to all 0 for now
// row, bg, ba set to 0
l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_17>();
l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_ADDRESS_0_13, TT::ARR0_DDR_ADDRESS_0_13_LEN>(0);
l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_1>();
l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_0>();
l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_BANK_0_1, TT::ARR0_DDR_BANK_0_1_LEN>(0);
l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_2>();

return instruction_t<T>(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1);
}

///
/// @brief Create, initialize an RCD (RCW - JEDEC) CCS command
/// @tparam T the target type of the chiplet which executes the CCS instruction
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41 changes: 1 addition & 40 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@

#include <p9_mc_scom_addresses.H>
#include <p9_mc_scom_addresses_fld.H>

#include <lib/phy/mss_lrdimm_training.H>
#include <lib/phy/mss_training.H>
#include <lib/dimm/rank.H>
Expand All @@ -48,8 +47,8 @@
#include <lib/ccs/ccs.H>
#include <lib/mc/port.H>
#include <lib/rosetta_map/rosetta_map.H>
#include <lib/workarounds/ccs_workarounds.H>
#include <lib/dimm/ddr4/pba.H>
#include <lib/eff_config/timing.H>

#ifdef LRDIMM_CAPABLE
#include <lib/phy/mss_lrdimm_training_helper.H>
Expand Down Expand Up @@ -692,44 +691,6 @@ uint64_t mrep::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_
return 0;
}

///
/// @brief Sets up and runs the calibration step
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode mwd::run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const
{
return fapi2::FAPI2_RC_SUCCESS;
}

///
/// @brief Executes a cal step with workarounds
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode mwd::execute( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const
{
return fapi2::FAPI2_RC_SUCCESS;
}

///
/// @brief Calculates the number of cycles a given calibration step will take
/// @param[in] i_target - the MCA target on which to operate
/// @return l_cycles - the number of cycles a given calibration step wil take
///
uint64_t mwd::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const
{
return 0;
}

///
/// @brief Deconfigures calibration steps depending upon LRDIMM type
/// @param[in] i_dimm_type - DIMM type
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45 changes: 0 additions & 45 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H
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Original file line number Diff line number Diff line change
Expand Up @@ -608,51 +608,6 @@ class mrep : public step

};

///
/// @brief MPR training step
///
class mwd : public step
{
public:
mwd() :
step("MWD")
{}

///
/// @brief Default virtual destructor
///
~mwd() = default;

///
/// @brief Sets up and runs the calibration step
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode run( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const;

///
/// @brief Executes a cal step with workarounds
/// @param[in] i_target - the MCA target on which to operate
/// @param[in] i_rp - the rank pair
/// @param[in] i_abort_on_error - whether or not we are aborting on cal error
/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok
///
fapi2::ReturnCode execute( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
const uint64_t i_rp,
const uint8_t i_abort_on_error ) const;

///
/// @brief Calculates the number of cycles a given calibration step will take
/// @param[in] i_target - the MCA target on which to operate
/// @return l_cycles - the number of cycles a given calibration step wil take
///
uint64_t calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) const;
};

// TK:LRDIMM Identify if Host Interface Write Leveling (HWL) Mode needs to be updated or if the PHY can handle it
// TK:LRDIMM Identify if Host Interface Read Training is any different
// TK:LRDIMM Identify if Host Interface Write training Training is any different
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12 changes: 12 additions & 0 deletions src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C
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Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,7 @@
#ifdef LRDIMM_CAPABLE
#include <lib/phy/mss_dwl.H>
#include <lib/phy/mss_mrd_fine.H>
#include <lib/phy/mss_mwd_coarse.H>
#endif

namespace mss
Expand Down Expand Up @@ -1248,6 +1249,17 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>&
l_steps.push_back(std::make_shared<wr_lvl>(i_sim));
}

#ifdef LRDIMM_CAPABLE

//MWD COARSE
if(i_cal_steps.getBit<mss::cal_steps::MWD_COARSE>())
{
FAPI_INF("LRDIMM: MWD COARSE is enabled");
l_steps.push_back(std::make_shared<mss::training::lrdimm::mwd_coarse>());
}

#endif

// INITIAL_PAT_WR
if(i_cal_steps.getBit<mss::cal_steps::INITIAL_PAT_WR>())
{
Expand Down

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