p9_ppe_commands: add -step_trap support

Change-Id: I734f2cafae2d6cb67b909459b80266052a988542
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31451
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42287
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.H

@@ -64,12 +64,12 @@ typedef struct
 /**
  * @brief Offsets from base address for XIRs.
  */
-const static uint64_t PPE_XIXCR    = 0x0;
-const static uint64_t PPE_XIRAMRA  = 0x1;
-const static uint64_t PPE_XIRAMGA  = 0x2;
-const static uint64_t PPE_XIRAMDBG = 0x3;
-const static uint64_t PPE_XIRAMEDR = 0x4;
-const static uint64_t PPE_XIDBGPRO = 0x5;
+const static uint64_t PPE_XIXCR    = 0x0; //XCR_NONE
+const static uint64_t PPE_XIRAMRA  = 0x1; //XCR_SPRG0
+const static uint64_t PPE_XIRAMGA  = 0x2; //IR_SPRG0
+const static uint64_t PPE_XIRAMDBG = 0x3; //XSR_SPRG0
+const static uint64_t PPE_XIRAMEDR = 0x4; //IR_EDR
+const static uint64_t PPE_XIDBGPRO = 0x5; //XSR_IAR
 
 enum PPE_DUMP_MODE
 {