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Updated pcie_scominit and pcie_config to manage systems not using PEC…
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… STACK0.

Defect SW417485 used to track these changes.

Change-Id: I945ccd7726e2938fa07e8e3b118fc17e97111544
CQ: SW417485
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56909
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57062
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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ricmata authored and dcrowell77 committed Apr 21, 2018
1 parent 1bad3f8 commit ff5baff
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Showing 2 changed files with 69 additions and 2 deletions.
58 changes: 57 additions & 1 deletion src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C
Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,13 @@ const uint64_t PCI_PFIR_ACTION0_REG = 0xB000000000000000ULL;
const uint64_t PCI_PFIR_ACTION1_REG = 0xB000000000000000ULL;
const uint64_t PCI_PFIR_MASK_REG = 0x0E00000000000000ULL;

// PEC IOVALID constants
const uint8_t PEC0_IOP_IOVALID_PHB0_MASK = 1;
const uint8_t PEC1_IOP_IOVALID_PHB1_MASK = 2;
const uint8_t PEC1_IOP_IOVALID_PHB2_MASK = 1;
const uint8_t PEC2_IOP_IOVALID_PHB3_MASK = 4;
const uint8_t PEC2_IOP_IOVALID_PHB4_MASK = 2;
const uint8_t PEC2_IOP_IOVALID_PHB5_MASK = 1;

//------------------------------------------------------------------------------
// Function definitions
Expand All @@ -93,6 +100,9 @@ fapi2::ReturnCode p9_pcie_config(
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;

fapi2::buffer<uint64_t> l_buf = 0;
uint8_t pec0_iovalid_bits = 0;
uint8_t pec1_iovalid_bits = 0;
uint8_t pec2_iovalid_bits = 0;
uint8_t l_attr_proc_pcie_iovalid_enable = 0;
std::vector<uint64_t> l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m;
uint64_t l_base_addr_mmio;
Expand Down Expand Up @@ -163,6 +173,21 @@ fapi2::ReturnCode p9_pcie_config(
l_attr_proc_pcie_iovalid_enable));
FAPI_DBG("l_attr_proc_pcie_iovalid_enable: %#x", l_attr_proc_pcie_iovalid_enable);

if (l_pec_id == 0)
{
pec0_iovalid_bits = l_attr_proc_pcie_iovalid_enable;
}

if (l_pec_id == 1)
{
pec1_iovalid_bits = l_attr_proc_pcie_iovalid_enable;
}

if (l_pec_id == 2)
{
pec2_iovalid_bits = l_attr_proc_pcie_iovalid_enable;
}

// configure extended addressing facility
if (l_extended_addressing_mode)
{
Expand Down Expand Up @@ -278,7 +303,7 @@ fapi2::ReturnCode p9_pcie_config(
l_buf.setBit<PEC_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN>();
l_buf.insertFromRight<PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT,
PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN>(PEC_AIB_HWCFG_OSBM_HOL_BLK_CNT);
FAPI_DBG("PECc%i: %#lx", l_pec_id, l_buf());
FAPI_DBG("PEC%i: %#lx", l_pec_id, l_buf());
FAPI_TRY(fapi2::putScom(l_pec_chiplet, PEC_PBAIBHWCFG_REG, l_buf));
}

Expand All @@ -297,6 +322,37 @@ fapi2::ReturnCode p9_pcie_config(
l_phb_id),
"Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");

// Initialize PHBs with IOVALID set (SW417485)
if ((l_phb_id == 0) && !(pec0_iovalid_bits & PEC0_IOP_IOVALID_PHB0_MASK))
{
continue;
}

if ((l_phb_id == 1) && !(pec1_iovalid_bits & PEC1_IOP_IOVALID_PHB1_MASK))
{
continue;
}

if ((l_phb_id == 2) && !(pec1_iovalid_bits & PEC1_IOP_IOVALID_PHB2_MASK))
{
continue;
}

if ((l_phb_id == 3) && !(pec2_iovalid_bits & PEC2_IOP_IOVALID_PHB3_MASK))
{
continue;
}

if ((l_phb_id == 4) && !(pec2_iovalid_bits & PEC2_IOP_IOVALID_PHB4_MASK))
{
continue;
}

if ((l_phb_id == 5) && !(pec2_iovalid_bits & PEC2_IOP_IOVALID_PHB5_MASK))
{
continue;
}

if (!l_hw363246)
{
// Phase2 init step 12_a
Expand Down
13 changes: 12 additions & 1 deletion src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -64,6 +64,9 @@ const uint8_t PEC2_IOP_SWAP_START_BIT = 7;
const uint8_t PEC0_IOP_IOVALID_ENABLE_START_BIT = 4;
const uint8_t PEC1_IOP_IOVALID_ENABLE_START_BIT = 4;
const uint8_t PEC2_IOP_IOVALID_ENABLE_START_BIT = 4;
const uint8_t PEC_IOP_IOVALID_ENABLE_STACK0_BIT = 4;
const uint8_t PEC_IOP_IOVALID_ENABLE_STACK1_BIT = 5;
const uint8_t PEC_IOP_IOVALID_ENABLE_STACK2_BIT = 6;
const uint8_t PEC_IOP_REFCLOCK_ENABLE_START_BIT = 32;
const uint8_t PEC_IOP_PMA_RESET_START_BIT = 29;
const uint8_t PEC_IOP_PIPE_RESET_START_BIT = 28;
Expand Down Expand Up @@ -257,6 +260,14 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
PEC1_IOP_IOVALID_ENABLE_START_BIT, PEC1_IOP_BIT_COUNT,
PEC2_IOP_IOVALID_ENABLE_START_BIT, PEC2_IOP_BIT_COUNT));
FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());

// Set IOVALID for base PHB if PHB2, or PHB4, or PHB5 are set (SW417485)
if ((l_buf.getBit(PEC_IOP_IOVALID_ENABLE_STACK1_BIT)) || (l_buf.getBit(PEC_IOP_IOVALID_ENABLE_STACK2_BIT)))
{
l_buf.setBit<PEC_IOP_IOVALID_ENABLE_STACK0_BIT>();
}

FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf),
"Error from putScom (0x%.16llX), PEC_CPLT_CONF1_OR");

Expand Down

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