Setup PCIe bus configuration · open-power/nicole-xml@26b2092 · GitHub

Commit

Setup PCIe bus configuration

Browse files

Changed to be consistent with the schematics.

CPU0/E0/A/x16: Backplane
CPU0/E1/A/x2:  Broadcom
CPU0/E1/B/x4:  m.2 SSD
CPU0/E2/A/X16: Backplane
CPU1/E0/A/x16: Unused
CPU1/E1/A/x8:  Unused
CPU1/E1/B/x4:  Unused
CPU1/E2/A/x4:  m.2 SSD
CPU1/E2/B/x1:  Aspeed (VGA)
CPU1/E2/C/x1:  USB

Signed-off-by: Artem Senichev <a.senichev@yadro.com>

Loading branch information

Artem Senichev committed Jul 4, 2019

1 parent 92d3a46 commit 26b2092