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WOF: Function to calculate VDD/VDN step number
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1. Calculate VDN/VDD step number
2. Extract the WOF header address from the PGPE header
3. Save important data from WOF header into global struct
4. Create global pointer struct to save important addresses
   to a pinned location in memory.

Change-Id: I2249777134608d9f79bdc85692a3acbf7907c3f5
RTC:130216
Depends-on: Ic323321b8c66945732a6b7345ad85d6f41a62edd
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34300
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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@aalugore @wilbryan
aalugore authored and wilbryan committed Feb 1, 2017
1 parent 11bf85d commit 009f439
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Showing 8 changed files with 345 additions and 21 deletions.
1 change: 0 additions & 1 deletion src/include/proc_shared.h
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,6 @@
#include "gpe_export.h"

// Paramaters for gpe_get_core_data()

typedef struct ipc_core_data_parms
{
GpeErrorStruct error;
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16 changes: 9 additions & 7 deletions src/occ_405/amec/amec_slave_smh.c
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Original file line number Diff line number Diff line change
Expand Up @@ -55,13 +55,13 @@
#include <amec_health.h>
#include <amec_analytics.h>
#include <common.h>
#include <occhw_async.h>
#include <wof.h>

//*************************************************************************
// Externs
//*************************************************************************
extern dcom_slv_inbox_t G_dcom_slv_inbox_rx;

//*************************************************************************
// Macros
//*************************************************************************
Expand Down Expand Up @@ -510,26 +510,28 @@ void amec_slv_state_4(void)
//-------------------------------------------------------
if( IS_OCC_STATE_ACTIVE() )
{
/* TODO: RTC: 166301 - Logic to determine if WOF algorithm should run.
static bool run_wof_algoritm = true;

if( !run_wof_algorithm )
/* TODO: RTC 166301 - Logic to determine if WOF algorithm should run.
// The WOF algorithm is to be run every 4ms. Since amec_slv_state_4
// is run every 2ms, we need to skip every other invocation.
static bool L_run_wof_algorithm = true;
if( !L_run_wof_algorithm )
{
// When false, the last invocation decided we need to wait 2 ms
// run wof algo next time.
run_wof_algorithm = true;
L_run_wof_algorithm = true;
}
else
{
//if IPC command is idle and ready to go
//{
//wof_main();
run_wof_algorithm = false;
L_run_wof_algorithm = false;
//}
//else if IPC command is still waiting
//make thread wait another 2 ms
//{
// run_wof_algorithm = true;
// L_run_wof_algorithm = true;
//}
//else if IPC command is returning an error
//{
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33 changes: 28 additions & 5 deletions src/occ_405/linkocc.cmd
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -533,14 +533,36 @@ SECTIONS
#if EXECUTABLE_FREE_SPACE
_DATA_SECTION_SIZE = . - _DATA_SECTION_BASE;
__WRITEABLE_DATA_LEN__ = . - __WRITEABLE_DATA_ADDR__ ;
_EX_FREE_SECTION_SIZE = _TRACE_BUFFERS_START_BASE - _EX_FREE_SECTION_BASE;
_EX_FREE_SECTION_SIZE = _GLOBAL_DATA_BASE - _EX_FREE_SECTION_BASE;
#else
_DATA_SECTION_SIZE = _TRACE_BUFFERS_START_BASE - _DATA_SECTION_BASE;
__WRITEABLE_DATA_LEN__ = _TRACE_BUFFERS_START_BASE - __WRITEABLE_DATA_ADDR__ ;
_DATA_SECTION_SIZE = _GLOBAL_DATA_BASE - _DATA_SECTION_BASE;
__WRITEABLE_DATA_LEN__ = _GLOBAL_DATA_BASE - __WRITEABLE_DATA_ADDR__ ;
_EX_FREE_SECTION_SIZE = 0;
#endif

_SSX_FREE_END = _TRACE_BUFFERS_START_BASE - 1;
_SSX_FREE_END = _GLOBAL_DATA_BASE - 1;


////////////////////////////////
// Global Data Section
//
// Contains pointers to important Global variables
//
////////////////////////////////
__CUR_COUNTER__ = .;
_GLOBAL_DATA_BASE = 0xfffb3f00;
_GLOBAL_DATA_SIZE = 0x100;
. = _GLOBAL_DATA_BASE;
#if !PPC405_MMU_SUPPORT
. = . - writethrough_offset;
_LMA = . + writethrough_offset;
.global_data . : AT(_LMA) {*(global_data) . = ALIGN(_GLOBAL_DATA_SIZE);}
. = . + writethrough_offset;
#else
.global_data . : {*(global_data) . = ALIGN(_GLOBAL_DATA_SIZE);} > sram
#endif
. = __CUR_COUNTER__;


////////////////////////////////
// Trace Buffers
Expand Down Expand Up @@ -668,3 +690,4 @@ SECTIONS
_PPC405_END_OF_MEMORY = 0;
}


156 changes: 153 additions & 3 deletions src/occ_405/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -60,6 +60,7 @@
#include <pgpe_shared.h>
#include <gpe_register_addresses.h>
#include <p9_pstates_occ.h>
#include <wof.h>

extern uint32_t __ssx_boot; // Function address is 32 bits
extern uint32_t G_occ_phantom_critical_count;
Expand All @@ -76,6 +77,19 @@ extern apss_complete_args_t G_gpe_complete_pwr_meas_read_args;

extern uint32_t G_pgpe_beacon_address;

extern uint32_t G_proc_fmin_khz;
extern uint32_t G_proc_fmax_khz;
extern uint32_t G_wof_active_quads_sram_addr;
extern uint32_t G_wof_tables_main_mem_addr;
extern uint32_t G_wof_tables_len;
extern bool G_run_wof_main;
extern wof_header_data_t G_wof_header;

extern uint32_t G_khz_per_pstate;

extern uint8_t G_proc_pmin;
extern uint8_t G_proc_pmax;

IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,ID_NUM_INVALID);

// PGPE Image Header Parameters
Expand All @@ -87,9 +101,11 @@ OCCPstateParmBlock G_oppb; // OCC Pstate Parameters Block Structure
extern uint16_t G_proc_fmax_mhz; // max(turbo,uturbo) frequencies


//Set main thread timer for one second
// Set main thread timer for one second
#define MAIN_THRD_TIMER_SLICE ((SsxInterval) SSX_SECONDS(1))



// SIMICS printf/printk
SimicsStdio G_simics_stdout;
SimicsStdio G_simics_stderr;
Expand All @@ -98,6 +114,8 @@ SimicsStdio G_simics_stderr;
uint8_t G_noncritical_stack[NONCRITICAL_STACK_SIZE];
uint8_t G_critical_stack[CRITICAL_STACK_SIZE];



//NOTE: Three semaphores are used so that if in future it is decided
// to move health monitor and FFDC into it's own threads, then
// it can be done easily without more changes.
Expand Down Expand Up @@ -458,6 +476,120 @@ void create_tlb_entry(uint32_t address, uint32_t size)
}


/*
* Function Specification
*
* Name: read_wof_header
*
* Description: Read WOF Tables header and populate global variables
* needed for WOF
*
* End Function Specification
*/
void read_wof_header(void)
{
int l_ssxrc = SSX_OK;
uint32_t l_reasonCode = 0;
uint32_t l_extReasonCode = 0;

do
{
// use block copy engine to read WOF header
BceRequest l_wof_header_req;

// 128 byte aligned buffer to read the data
temp_bce_request_buffer_t l_temp_bce_buff = {{0}};

uint32_t pad = G_wof_tables_main_mem_addr%128;
// Force WOF tables address is on 128 byte boundary
uint32_t wof_main_mem_addr_128 = G_wof_tables_main_mem_addr - pad;
// Create request
l_ssxrc = bce_request_create(&l_wof_header_req, // block copy object
&G_pba_bcde_queue, // main to sram copy engine
wof_main_mem_addr_128, // mainstore address
(uint32_t) &l_temp_bce_buff, // SRAM start address
MIN_BCE_REQ_SIZE, // size of copy
SSX_WAIT_FOREVER, // no timeout
NULL, // no call back
NULL, // no call back args
ASYNC_REQUEST_BLOCKING);// blocking request

if(l_ssxrc != SSX_OK)
{
CMDH_TRAC_ERR("read_wof_header: BCDE request create failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_WOF_HEADER
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata2 Internal function checkpoint
* @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE
* @devdesc Failed to create BCDE request
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE;
break;
}


// Do the actual copy
l_ssxrc = bce_request_schedule(&l_wof_header_req);

if(l_ssxrc != SSX_OK)
{
CMDH_TRAC_ERR("read_wof_header: BCE request schedule failure rc=[%08X]", -l_ssxrc);
/*
* @errortype
* @moduleid READ_WOF_HEADER
* @reasoncode SSX_GENERIC_FAILURE
* @userdata1 RC for BCE block-copy engine
* @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE
* @devdesc Failed to read PPMR data by using BCDE
*/
l_reasonCode = SSX_GENERIC_FAILURE;
l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE;
break;
}

// Copy the data into Global WOF header struct
memcpy(&G_wof_header, &(l_temp_bce_buff.data[pad]), sizeof(wof_header_data_t));




}while( 0 );

// Check for errors and log, if any
if( l_ssxrc != SSX_OK )
{
errlHndl_t l_errl = createErrl(READ_WOF_HEADER, //modId
l_reasonCode, //reasoncode
l_extReasonCode, //Extended reason code
ERRL_SEV_UNRECOVERABLE, //Severity
NULL, //Trace Buf
0, //Trace Size
-l_ssxrc, //userdata1
0); //userdata2

// Callout firmware
addCalloutToErrl(l_errl,
ERRL_CALLOUT_TYPE_COMPONENT_ID,
ERRL_COMPONENT_ID_FIRMWARE,
ERRL_CALLOUT_PRIORITY_HIGH);

// Commit error log
commitErrl(&l_errl);

// We were unable to get the WOF header thus it should not be run.
G_run_wof_main = false;

return;

}
}



/*
* Function Specification
*
Expand All @@ -470,7 +602,6 @@ void create_tlb_entry(uint32_t address, uint32_t size)
*
* End Function Specification
*/

void read_pgpe_header(void)
{
uint64_t magic_number;
Expand Down Expand Up @@ -517,6 +648,20 @@ void read_pgpe_header(void)
MAIN_TRAC_IMP("Read PGPE Beacon Address[0x%08x]",
G_pgpe_beacon_address);

// Read active quads address, wof tables address, and wof tables len
G_wof_active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR);
G_wof_tables_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR);
G_wof_tables_len = in32(PGPE_WOF_TBLS_LEN_PTR);

MAIN_TRAC_IMP("Read WOF Tables Main Memory Address[0x%08x], Len[0x%08x],"
" Active Quads Address[0x%08x]",
G_wof_tables_main_mem_addr,
G_wof_tables_len,
G_wof_active_quads_sram_addr );

// Extract important WOF data into global space
read_wof_header();

// Read OCC/PGPE Shared SRAM address and size
G_pgpe_shared_sram_address = in32(PGPE_SHARED_SRAM_ADDR_PTR);
G_pgpe_shared_sram_sz = in32(PGPE_SHARED_SRAM_SZ_PTR);
Expand Down Expand Up @@ -742,6 +887,11 @@ void read_oppb_params(const OCCPstateParmBlock* oppb_offset)
}
} while (0);

// Read WOF addresses

MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]",
G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz);

if ( l_ssxrc != SSX_OK )
{
errlHndl_t l_errl = createErrl(READ_OPPB_PARAMS, //modId
Expand Down
3 changes: 2 additions & 1 deletion src/occ_405/occ_service_codes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -266,6 +266,7 @@ enum occModuleId
READ_PPMR_HEADER = MAIN_COMP_ID | 0x13,
READ_OPPB_PARAMS = MAIN_COMP_ID | 0x14,
MAIN_SMGR_MID = MAIN_COMP_ID | 0x15,
READ_WOF_HEADER = MAIN_COMP_ID | 0x16,
};

enum occUserDataType
Expand Down
11 changes: 10 additions & 1 deletion src/occ_405/pgpe/pgpe_shared.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* Contributors Listed Below - COPYRIGHT 2011,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand All @@ -32,6 +32,9 @@
#define PGPE_SHARED_SRAM_ADDR_OFFSET 0x0c
#define PGPE_SHARED_SRAM_SZ_OFFSET 0x14
#define PGPE_BEACON_ADDR_OFFSET 0x48
#define PGPE_ACTIVE_QUAD_ADDR_OFFSET 0x4c
#define PGPE_WOF_TBLS_ADDR_OFFSET 0x50
#define PGPE_WOF_TBLS_LEN_OFFSET 0x54

// PGPE Image Header Parameter addresses

Expand All @@ -42,6 +45,12 @@
// A pointer to PGPE Beacon Address
#define PGPE_BEACON_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_BEACON_ADDR_OFFSET)

// Pointers to data needed by WOF
#define PGPE_ACTIVE_QUAD_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_ACTIVE_QUAD_ADDR_OFFSET)
#define PGPE_WOF_TBLS_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_ADDR_OFFSET)
#define PGPE_WOF_TBLS_LEN_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_LEN_OFFSET)



// PMMR (Pstates PM region) in HOMMR
#define PPMR_OPPM_ADDR_OFFSET 0x40 //offset of the OCC Pstates Parameter Block address in the PPMR header
Expand Down
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