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Add support for memory config command version 0x21
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the OCC maintains support for version 0x20

Change-Id: I06e637db202602e3823ffeceb56d482545b1016a
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36733
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Tested-by: Wael El-Essawy <welessa@us.ibm.com>
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@essawy
essawy committed Feb 23, 2017
1 parent cfdf01a commit ddf83aa
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Showing 5 changed files with 101 additions and 28 deletions.
82 changes: 62 additions & 20 deletions src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,7 @@
#include "amec_sys.h"
#include <centaur_data.h>
#include "dimm.h"
#include "memory.h"
#include <avsbus.h>
#include "p9_pstates_occ.h"

Expand All @@ -63,6 +64,7 @@
#define DATA_IPS_VERSION 0

#define DATA_MEM_CFG_VERSION_20 0x20
#define DATA_MEM_CFG_VERSION_21 0x21

#define DATA_MEM_THROT_VERSION_20 0x20

Expand Down Expand Up @@ -1605,7 +1607,7 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
cmdh_fsp_rsp_t * o_rsp_ptr)
{
errlHndl_t l_err = NULL;
cmdh_mem_cfg_v20_t* l_cmd_ptr = (cmdh_mem_cfg_v20_t*)i_cmd_ptr;
cmdh_mem_cfg_v21_t* l_cmd_ptr = (cmdh_mem_cfg_v21_t*)i_cmd_ptr;
uint16_t l_data_length = 0;
uint16_t l_exp_data_length = 0;
uint8_t l_num_centaurs = 0;
Expand All @@ -1614,6 +1616,8 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
uint8_t l_i2c_port;
uint8_t l_i2c_addr = 0;
uint8_t l_dimm_num = 0;
uint8_t num_data_sets = 0;
cmdh_mem_cfg_data_set_t* data_sets_ptr;
int i;

do
Expand All @@ -1633,53 +1637,91 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
}

// Process data based on version
if(l_cmd_ptr->header.version == DATA_MEM_CFG_VERSION_20)
if( l_cmd_ptr->header.version == DATA_MEM_CFG_VERSION_20 ||
l_cmd_ptr->header.version == DATA_MEM_CFG_VERSION_21 )
{
// Verify the actual data length matches the expected data length for this version
l_exp_data_length = sizeof(cmdh_mem_cfg_header_t) - sizeof(cmdh_fsp_cmd_header_t) +
(l_cmd_ptr->header.num_data_sets * sizeof(cmdh_mem_cfg_data_set_v20_t));
if(l_cmd_ptr->header.version == DATA_MEM_CFG_VERSION_21)
{
G_sysConfigData.ips_mem_pwr_ctl = l_cmd_ptr->header.ips_mem_pwr_ctl;
G_sysConfigData.default_mem_pwr_ctl = l_cmd_ptr->header.default_mem_pwr_ctl;

num_data_sets = ((cmdh_mem_cfg_v21_t*) l_cmd_ptr)->header.num_data_sets;
data_sets_ptr = ((cmdh_mem_cfg_v21_t*) l_cmd_ptr)->data_set;

// Verify the actual data length matches the expected data length for this version
l_exp_data_length = sizeof(cmdh_mem_cfg_header_v21_t) - sizeof(cmdh_fsp_cmd_header_t) +
(num_data_sets * sizeof(cmdh_mem_cfg_data_set_t));

}

else if(l_cmd_ptr->header.version == DATA_MEM_CFG_VERSION_20)
{
// OFF memory power control means none of the
// memory control registers are ever updated.
G_sysConfigData.ips_mem_pwr_ctl = MEM_PWR_CTL_NO_SUPPORT;
G_sysConfigData.default_mem_pwr_ctl = MEM_PWR_CTL_NO_SUPPORT;

num_data_sets = ((cmdh_mem_cfg_v20_t*) l_cmd_ptr)->header.num_data_sets;
data_sets_ptr = ((cmdh_mem_cfg_v20_t*) l_cmd_ptr)->data_set;

// Verify the actual data length matches the expected data length for this version
l_exp_data_length = sizeof(cmdh_mem_cfg_header_v20_t) - sizeof(cmdh_fsp_cmd_header_t) +
(num_data_sets * sizeof(cmdh_mem_cfg_data_set_t));
}


if(l_exp_data_length != l_data_length)
{
CMDH_TRAC_ERR("data_store_mem_cfg: Invalid mem config data packet: data_length[%u] exp_length[%u] version[0x%02X] num_data_sets[%u]",
l_data_length,
l_exp_data_length,
l_cmd_ptr->header.version,
l_cmd_ptr->header.num_data_sets);
CMDH_TRAC_ERR("data_store_mem_cfg: Invalid mem config data packet: "
"data_length[%u] exp_length[%u] version[0x%02X] num_data_sets[%u]",
l_data_length,
l_exp_data_length,
l_cmd_ptr->header.version,
num_data_sets);

cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
break;
}

if (l_cmd_ptr->header.num_data_sets > 0)
if (num_data_sets > 0)
{
// Store the memory type. Memory must all be the same type, save from first and verify remaining
G_sysConfigData.mem_type = l_cmd_ptr->data_set[0].memory_type;
G_sysConfigData.mem_type = data_sets_ptr[0].memory_type;
if(G_sysConfigData.mem_type == MEM_TYPE_NIMBUS)
{
// Nimbus type -- dimm_info1 is I2C engine which must be the same
// save from first entry and verify remaining
G_sysConfigData.dimm_i2c_engine = l_cmd_ptr->data_set[0].dimm_info1;
G_sysConfigData.dimm_i2c_engine = data_sets_ptr[0].dimm_info1;
}
else
{
// TODO: RTC 163359 - OCC Centaur Support
//G_sysConfigData.mem_type = MEM_TYPE_CUMULUS;

CMDH_TRAC_ERR("data_store_mem_cfg: Invalid mem type 0x%02X in config data packet version[0x%02X] num_data_sets[%u]",
l_cmd_ptr->data_set[0].memory_type,
data_sets_ptr[0].memory_type,
l_cmd_ptr->header.version,
l_cmd_ptr->header.num_data_sets);
num_data_sets);

cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
break;
}

// Store the hardware sensor ID and the temperature sensor ID
for(i=0; i<l_cmd_ptr->header.num_data_sets; i++)
for(i=0; i<num_data_sets; i++)
{
cmdh_mem_cfg_v20_t* l_cmd2_ptr = (cmdh_mem_cfg_v20_t*)i_cmd_ptr;
cmdh_mem_cfg_data_set_v20_t* l_data_set = &l_cmd2_ptr->data_set[i];
cmdh_mem_cfg_data_set_t* l_data_set;

if(l_cmd_ptr->header.version == DATA_MEM_CFG_VERSION_21)
{
cmdh_mem_cfg_v21_t* l_cmd2_ptr = (cmdh_mem_cfg_v21_t*)i_cmd_ptr;
l_data_set = &l_cmd2_ptr->data_set[i];
}
else // DATA_MEM_CFG_VERSION_20
{
cmdh_mem_cfg_v20_t* l_cmd2_ptr = (cmdh_mem_cfg_v20_t*)i_cmd_ptr;
l_data_set = &l_cmd2_ptr->data_set[i];
}

// Verify matching memory type and process based on memory type
if( (l_data_set->memory_type == G_sysConfigData.mem_type) &&
Expand Down Expand Up @@ -1825,7 +1867,7 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
G_sysConfigData.mem_type, l_num_centaurs, l_num_dimms);

// No errors so we can enable memory monitoring if the data indicates it should be enabled
if(l_cmd_ptr->header.num_data_sets == 0) // num data sets of 0 indicates memory monitoring disabled
if(num_data_sets == 0) // num data sets of 0 indicates memory monitoring disabled
{
CMDH_TRAC_IMP("Memory monitoring is not allowed (mem config data sets = 0)");
}
Expand All @@ -1838,7 +1880,7 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
// Require the mem throt packet for going to active state
SMGR_VALIDATE_DATA_ACTIVE_MASK |= DATA_MASK_MEM_THROT;

CMDH_TRAC_IMP("Memory monitoring is allowed (mem config data sets = %d)", l_cmd_ptr->header.num_data_sets);
CMDH_TRAC_IMP("Memory monitoring is allowed (mem config data sets = %d)", num_data_sets);
}
}
else
Expand Down
31 changes: 24 additions & 7 deletions src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -261,10 +261,21 @@ typedef struct __attribute__ ((packed))
typedef struct __attribute__ ((packed))
{
struct cmdh_fsp_cmd_header;
uint8_t format;
uint8_t version;
uint8_t num_data_sets;
}cmdh_mem_cfg_header_t;
uint8_t format;
uint8_t version;
uint8_t num_data_sets;
}cmdh_mem_cfg_header_v20_t;

// Header data for mem cfg packet
typedef struct __attribute__ ((packed))
{
struct cmdh_fsp_cmd_header;
uint8_t format;
uint8_t version;
uint8_t default_mem_pwr_ctl; // default memory power control
uint8_t ips_mem_pwr_ctl; // Idle Power Save memory power control
uint8_t num_data_sets;
}cmdh_mem_cfg_header_v21_t;

// Config packet definition used by TMGT to
// send sensor mappings for centaurs and dimms
Expand All @@ -277,14 +288,20 @@ typedef struct __attribute__ ((packed))
uint8_t dimm_info1;
uint8_t dimm_info2;
uint8_t dimm_info3;
}cmdh_mem_cfg_data_set_v20_t;
}cmdh_mem_cfg_data_set_t;

typedef struct __attribute__ ((packed))
{
cmdh_mem_cfg_header_t header;
cmdh_mem_cfg_data_set_v20_t data_set[1];
cmdh_mem_cfg_header_v20_t header;
cmdh_mem_cfg_data_set_t data_set[1];
}cmdh_mem_cfg_v20_t;

typedef struct __attribute__ ((packed))
{
cmdh_mem_cfg_header_v21_t header;
cmdh_mem_cfg_data_set_t data_set[1];
}cmdh_mem_cfg_v21_t;


// Header data for mem throttle packet
typedef struct __attribute__ ((packed))
Expand Down
2 changes: 2 additions & 0 deletions src/occ_405/occ_sys_config.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,8 @@ occSysConfigData_t G_sysConfigData =
.dimm_huids = {{0,0,0,0,0,0,0,0},{0,0,0,0,0,0,0,0}},
.mem_type = MEM_TYPE_NIMBUS,
.dimm_i2c_engine = PIB_I2C_ENGINE_E,
.ips_mem_pwr_ctl = MEM_PWR_CTL_OFF,
.default_mem_pwr_ctl = MEM_PWR_CTL_OFF,

// -------------------------------------------------------------------
// Memory Throttle Limits Initialization (for both Nimbus and Cumulus)
Expand Down
12 changes: 12 additions & 0 deletions src/occ_405/occ_sys_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -280,6 +280,16 @@ typedef struct
uint16_t reserved3; //reserved
} mem_throt_config_data_t;

// this enum defines memory power control
typedef enum
{
MEM_PWR_CTL_OFF = 0x00,
MEM_PWR_CTL_POWER_DOWN = 0x01,
MEM_PWR_CTL_PD_AND_STR = 0x02,
MEM_PWR_CTL_PD_AND_STR_CLK_STOP = 0x03,
MEM_PWR_CTL_NO_SUPPORT = 0xFF,
} eMemoryPowerControlSetting;


// Sys Config Structure

Expand Down Expand Up @@ -390,6 +400,8 @@ typedef struct
uint32_t dimm_huids[MAX_NUM_CENTAURS][NUM_DIMMS_PER_CENTAUR];
uint8_t mem_type;
uint8_t dimm_i2c_engine;
eMemoryPowerControlSetting ips_mem_pwr_ctl; // IPS memory power control
eMemoryPowerControlSetting default_mem_pwr_ctl; // default memory power control

// --------------------------------------
// Memory Throttle limits
Expand Down
2 changes: 1 addition & 1 deletion src/occ_405/proc/proc_pstate.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ typedef struct __attribute__ ((packed))
uint8_t reserved[16]; // Reserved static space: 16B
opal_pstate_data_t pstates[PSTATE_ENTRIES]; // Generated Pstates Table: 2048B
uint8_t max_pstate[24]; // Maximum Pstate with N active cores is max_pstate[N-1]: 24B
uint8_t pad[56]; // Padding in reserved static space: 56B
uint8_t pad[80]; // Padding in reserved static space: 80B
} opal_static_table_t __attribute__ ((aligned (128)));


Expand Down

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