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STOP: remove union usage in p9_pm_hcd_flags.h
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Change-Id: Ic57a5c5e604c45dcfdc720fd1205c7b6790c77e2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46157
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46160
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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@davidduyue @sgupta2m
davidduyue authored and sgupta2m committed Sep 20, 2017
1 parent c9a1884 commit 0005004
Showing 1 changed file with 38 additions and 156 deletions.
194 changes: 38 additions & 156 deletions src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h
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Expand Up @@ -38,105 +38,6 @@
#ifndef _P9_PM_HCDFLAGS_H_
#define _P9_PM_HCDFLAGS_H_

//OCC FLag defines
typedef union occ_flags
{
uint32_t value;
struct
{
#ifdef _BIG_ENDIAN
uint16_t high_order;
uint16_t low_order;
#else
uint16_t low_order;
uint16_t high_order;
#endif // _BIG_ENDIAN
} halfwords;
struct
{
#ifdef _BIG_ENDIAN
uint32_t pgpe_StartNonStop : 1;
uint32_t pgpe_PStateProtocolAutoActivate : 1;
uint32_t pgpe_PStateSafeMode : 1;
uint32_t pm_ComplexSuspend : 1;
uint32_t reserved1 : 4;
uint32_t sgpe_Active : 1;
uint32_t sgpe_IgnoreStopExits : 1;
uint32_t sgpe_IgnoreStopEntry : 1;
uint32_t sgpe_StopExitsIgnored : 1;
uint32_t sgpe_StopEntryIgnored : 1;
uint32_t reserved2 : 1;
uint32_t sgpe_Aux_Activate : 1;
uint32_t sgpe_Aux_Active : 1;
uint32_t pib_I2CMasterEngine1Lock : 2;
uint32_t pib_I2CMasterEngine2Lock : 2;
uint32_t pib_I2CMasterEngine3Lock : 2;
uint32_t undefined : 8;
uint32_t requested_ActiveQuadUpdate : 1;
uint32_t requested_OccSafeState : 1;
#else
uint32_t requested_OccSafeState : 1;
uint32_t requested_ActiveQuadUpdate : 1;
uint32_t undefined : 8;
uint32_t pib_I2CMasterEngine3Lock : 2;
uint32_t pib_I2CMasterEngine2Lock : 2;
uint32_t pib_I2CMasterEngine1Lock : 2;
uint32_t sgpe_Aux_Active : 1;
uint32_t sgpe_Aux_Activate : 1;
uint32_t reserved2 : 1;
uint32_t sgpe_StopEntryIgnored : 1;
uint32_t sgpe_StopExitsIgnored : 1;
uint32_t sgpe_IgnoreStopEntry : 1;
uint32_t sgpe_IgnoreStopExits : 1;
uint32_t sgpe_Active : 1;
uint32_t reserved1 : 4;
uint32_t pm_ComplexSuspend : 1;
uint32_t pgpe_PStateSafeMode : 1;
uint32_t pgpe_PStateProtocolAutoActivate : 1;
uint32_t pgpe_StartNonStop : 1;
#endif // _BIG_ENDIAN
} fields;
} occ_flags_t;

typedef union pgpe_flags
{
uint16_t value;
struct
{
#ifdef _BIG_ENDIAN
uint16_t resclk_enable : 1;
uint16_t ivrm_enable : 1;
uint16_t vdm_enable : 1;
uint16_t wof_enable : 1;
uint16_t dpll_dynamic_fmax_enable : 1;
uint16_t dpll_dynamic_fmin_enable : 1;
uint16_t dpll_droop_protect_enable : 1;
uint16_t reserved7 : 1;
uint16_t occ_ipc_immed_response : 1;
uint16_t wof_ipc_immed_response : 1;
uint16_t enable_fratio : 1;
uint16_t enable_vratio : 1;
uint16_t vratio_modifier : 1;
uint16_t reserved_13_15 : 3;
#else
uint16_t reserved_13_15 : 3;
uint16_t vratio_modifier : 1;
uint16_t enable_vratio : 1;
uint16_t enable_fratio : 1;
uint16_t wof_ipc_immed_response : 1;
uint16_t occ_ipc_immed_response : 1;
uint16_t reserved7 : 1;
uint16_t dpll_droop_protect_enable : 1;
uint16_t dpll_dynamic_fmin_enable : 1;
uint16_t dpll_dynamic_fmax_enable : 1;
uint16_t wof_enable : 1;
uint16_t vdm_enable : 1;
uint16_t ivrm_enable : 1;
uint16_t resclk_enable : 1;
#endif
} fields;
} pgpe_flags_t;


#ifndef __PPE_PLAT
namespace p9hcd
Expand All @@ -146,45 +47,45 @@ namespace p9hcd
//Enum form of OCC FLAGs.
enum PM_GPE_OCCFLG_DEFS
{
PGPE_START_NOT_STOP = 0,
PGPE_PSTATE_PROTOCOL_AUTO_ACTIVATE = 1,
PGPE_PSTATE_PROTOCOL_ACTIVATE = 1, // @todo PGPE Hcode dependencies
PGPE_SAFE_MODE = 2,
PM_COMPLEX_SUSPEND = 3,
SGPE_ACTIVE = 8,
SGPE_IGNORE_STOP_CONTROL = 9,
SGPE_IGNORE_STOP_ACTION = 10,
SGPE_IGNORE_STOP_EXITS = 11,
SGPE_IGNORE_STOP_ENTRIES = 12,
SGPE_24_7_ACTIVATE = 14,
SGPE_24_7_ACTIVE = 15,
PIB_I2C_MASTER_ENGINE_1_LOCK_BIT0 = 16, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_1_LOCK_BIT1 = 17, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_2_LOCK_BIT0 = 18, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_2_LOCK_BIT1 = 19, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_3_LOCK_BIT0 = 20, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_3_LOCK_BIT1 = 21, //BIT0 ored BIT1 gives the field
REQUESTED_ACTIVE_QUAD_UPDATE = 30,
REQUEST_OCC_SAFE_STATE = 31
PGPE_START_NOT_STOP = 0,
PGPE_PSTATE_PROTOCOL_AUTO_ACTIVATE = 1,
PGPE_PSTATE_PROTOCOL_ACTIVATE = 1, // @todo PGPE Hcode dependencies
PGPE_SAFE_MODE = 2,
PM_COMPLEX_SUSPEND = 3,
SGPE_ACTIVE = 8,
SGPE_IGNORE_STOP_CONTROL = 9,
SGPE_IGNORE_STOP_ACTION = 10,
SGPE_IGNORE_STOP_EXITS = 11,
SGPE_IGNORE_STOP_ENTRIES = 12,
SGPE_24_7_ACTIVATE = 14,
SGPE_24_7_ACTIVE = 15,
PIB_I2C_MASTER_ENGINE_1_LOCK_BIT0 = 16, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_1_LOCK_BIT1 = 17, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_2_LOCK_BIT0 = 18, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_2_LOCK_BIT1 = 19, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_3_LOCK_BIT0 = 20, //BIT0 ored BIT1 gives the field
PIB_I2C_MASTER_ENGINE_3_LOCK_BIT1 = 21, //BIT0 ored BIT1 gives the field
REQUESTED_ACTIVE_QUAD_UPDATE = 30,
REQUEST_OCC_SAFE_STATE = 31
};

//
//Enum form of OCC SCRATCH2.
//
enum PM_GPE_OCC_SCRATCH2_DEFS
{
PGPE_ACTIVE = 0,
PGPE_PSTATE_PROTOCOL_ACTIVE = 1,
PGPE_SAFE_MODE_ACTIVE = 2,
PM_COMPLEX_SUSPENDED = 3,
SPGE_DEBUG_TRAP_ENABLE = 8,
CME_DEBUG_TRAP_ENABLE = 9,
PGPE_DEBUG_TRAP_ENABLE = 10,
L3_CONTAINED_MODE = 11,
PGPE_SAFE_MODE_ERROR = 12,
PGPE_OP_TRACE_DISABLE = 24,
PGPE_OP_TRACE_MEM_MODE_START = 25,
PGPE_OP_TRACE_MEM_MODE_LENGTH = 2
PGPE_ACTIVE = 0,
PGPE_PSTATE_PROTOCOL_ACTIVE = 1,
PGPE_SAFE_MODE_ACTIVE = 2,
PM_COMPLEX_SUSPENDED = 3,
SPGE_DEBUG_TRAP_ENABLE = 8,
CME_DEBUG_TRAP_ENABLE = 9,
PGPE_DEBUG_TRAP_ENABLE = 10,
L3_CONTAINED_MODE = 11,
PGPE_SAFE_MODE_ERROR = 12,
PGPE_OP_TRACE_DISABLE = 24,
PGPE_OP_TRACE_MEM_MODE_START = 25,
PGPE_OP_TRACE_MEM_MODE_LENGTH = 2
};

//
Expand Down Expand Up @@ -220,39 +121,20 @@ enum PM_CME_FLAGS_DEFS
//
enum PM_CME_SCRATCH_DEFS
{
CME_SCRATCH_DB0_PROCESSING_ENABLE = 25,
CME_SCRATCH_LOCAL_PSTATE_IDX_START = 26,
CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH = 6
CME_SCRATCH_DB0_PROCESSING_ENABLE = 25,
CME_SCRATCH_LOCAL_PSTATE_IDX_START = 26,
CME_SCRATCH_LOCAL_PSTATE_IDX_LENGTH = 6
};


//
//Enum for of PGPE_HEADER_FLAGS
//
enum PM_PGPE_HEADER_FLAGS
{
PGPE_HEADER_FLAGS_RESCLK_ENABLE = 0,
PGPE_HEADER_FLAGS_IVRM_ENABLE = 1,
PGPE_HEADER_FLAGS_VDM_ENABLE = 2,
PGPE_HEADER_FLAGS_WOF_ENABLE = 3,
PGPE_HEADER_FLAGS_DPLL_DYNAMIC_FMAX_ENABLE = 4,
PGPE_HEADER_FLAGS_DPLL_DYNAMIC_FMIN_ENABLE = 5,
PGPE_HEADER_FLAGS_DPLL_DROOP_PROTECT_ENABLE = 6,
PGPE_HEADER_FLAGS_OCC_IPC_IMMEDIATE_MODE = 8,
PGPE_HEADER_FLAGS_WOF_IPC_IMMEDIATE_MODE = 9,
PGPE_HEADER_FLAGS_ENABLE_FRATIO = 10,
PGPE_HEADER_FLAGS_ENABLE_VRATIO = 11,
PGPE_HEADER_FLAGS_VRATIO_MODIFIER = 12
};

//
//Enum for of PPM Register Bits for FW Usage
//
enum PM_PPM_FW_FLAGS
{
CPPM_CPMMR_DISABLE_PERIODIC_CORE_QUIESCE = 2,
QPPM_QCCR_IGNORE_QUAD_STOP_EXITS = 10,
QPPM_QCCR_IGNORE_QUAD_STOP_ENTRIES = 11
CPPM_CPMMR_DISABLE_PERIODIC_CORE_QUIESCE = 2,
QPPM_QCCR_IGNORE_QUAD_STOP_EXITS = 10,
QPPM_QCCR_IGNORE_QUAD_STOP_ENTRIES = 11
};

#ifndef __PPE_PLAT
Expand Down

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