Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup

changes in this commit:

1) enable dpll lock checking in non-sim envrionment
2) change FAPI_DBG lines on set/reset sdis_n ops as
   removing prints saying they are DD1 only workaround
   due to they are permenant steps now
3) add missing content of p9_hcd_core_dcc_skewadjust
4) add DD2 sram_enable support (NOOP for DD1)

Change-Id: I9a87c9fb68bd3b8df156ca07ba384e38cac85e94
Original-Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719
Reviewed-by: Joseph E. Dery <dery@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -182,6 +182,24 @@
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Sdis_n set or clear : flushing LCBES condition woraround. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** --> 
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW388878</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>