PCIe updates for Nimbus DD2 GEN4 operation

  adjust REFISRC, REFISINK, VBGENDOC in PCIE PLL inits for all ECs
  set EDMOD in RX VGA Control Register 1 for DD2 only

Change-Id: I5ee30890c29110d767210546f62c3cb682f0e7cc
Original-Change-Id: Ib10b02fb49dbf7ccf8dcad2ada5ac463a927d4c7
CQ: HW414759
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42423
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Ricardo Mata <ricmata@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml

@@ -3262,6 +3262,24 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW414759</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD2.0 only -- apply PCI PLL and VGA gain EDGEMOD workarounds
+      to enable GEN4 operation
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
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