Add attribute engine algorithm for eff_config and pre_eff_config

Change-Id: I2c89e6da17511462afbc661680d19df18a4708f4
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72962
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80986
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Tested-by: RAJA DAS <rajadas2@in.ibm.com>

src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H

@@ -33,8 +33,8 @@
 // *HWP Level: 2
 // *HWP Consumed by: CI
 
-#ifndef EXP_CONSTS_H
-#define EXP_CONSTS_H
+#ifndef MSS_EXP_CONSTS_H
+#define MSS_EXP_CONSTS_H
 
 #include <generic/memory/lib/utils/shared/mss_generic_consts.H>
 
@@ -48,6 +48,30 @@ namespace exp
 
 constexpr uint32_t OCMB_ADDR_SHIFT = 3;
 
+///
+/// @brief enum list of explorer eff attributes to set
+///
+enum attr_eff_engine_fields
+{
+    // Template recursive base case
+    ATTR_EFF_BASE_CASE = 0,
+
+    // Attrs to set
+    BYTE_ENABLES = 1,
+    NIBBLE_ENABLES = 2,
+    SPD_TAA_MIN = 3,
+    FOUR_RANK_MODE = 4,
+    DDP_COMPATIBILITY = 5,
+    TSV_8H_SUPPORT = 6,
+    PSTATES = 7,
+    MRAM_SUPPORT = 8,
+    HEIGHT_3DS = 9,
+    SPD_CL_SUPPORTED = 10,
+
+    // Dispatcher set to last enum value
+    ATTR_EFF_DISPATCHER = SPD_CL_SUPPORTED,
+};
+
 ///
 /// @brief common explorer sizes
 ///
@@ -68,6 +92,18 @@ enum ffdc_codes
     EXP_I2C_SET_FIELD = 0x0001,
     READ_HOST_FW_RESPONSE_STRUCT = 0x0003,
     READ_SENSOR_CACHE_STRUCT = 0x0004,
+
+    SET_BYTE_ENABLES = 0x1041,
+    SET_NIBBLE_ENABLES = 0x1042,
+    SET_TAA_MIN = 0x1043,
+    SET_FOUR_RANK_MODE = 0x1044,
+    SET_DDP_COMPATIBILITY = 0x1045,
+    SET_TSV_8H_SUPPORT = 0x1046,
+    SET_VREF_DQ_TRAIN_RANGE = 0x1047,
+    SET_PSTATES = 0x1048,
+    SET_MRAM_SUPPORT = 0x1049,
+    SET_3DS_HEIGHT = 0x1050,
+    SET_SPD_CL_SUPPORTED = 0x1051,
 };
 
 ///

src/import/generic/memory/lib/utils/shared/mss_generic_consts.H

@@ -105,7 +105,7 @@ enum generic_ffdc_codes
     SET_ATTR_HYBRID = 0x1002,
     SET_ATTR_HYBRID_MEDIA = 0x1003,
     SET_ATTR_MASTER_RANKS = 0x1004,
-    PRE_DATA_ENGINE_CTOR = 0x1005,
+    SET_ATTR_RANKS_CONFIGED  = 0x1005,
     GET_FIELD = 0x1006,
     READ_SPD_FIELD = 0x1007,
     BASE_CFG_PARAM_SELECT = 0x1008,
@@ -144,9 +144,31 @@ enum generic_ffdc_codes
     SET_HYBRID_MEDIA = 0x1028,
     SET_MRANKS = 0x1029,
     SET_DIMM_RANKS_CNFG = 0x1039,
-
-    // SPD fields function codes
     DDIMM_RAWCARD_DECODE = 0x103a,
+    SET_DRAM_WIDTH = 0x1040,
+
+    SET_SI_VREF_DRAM_WR = 0x1041,
+    SET_SI_MC_RCV_IMP_DQ_DQS = 0x1042,
+    SET_SI_MC_DRV_IMP_DQ_DQS_PULL_UP = 0x1043,
+    SET_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN = 0x1044,
+    SET_SI_MC_DRV_SLEW_RATE_DQ_DQS = 0x1045,
+    SET_SI_MC_DRV_IMP_CMD_ADDR = 0x10466,
+    SET_SI_MC_DRV_SLEW_RATE_CMD_ADDR = 0x1047,
+    SET_SI_MC_DRV_IMP_CLK = 0x1048,
+    SET_SI_MC_DRV_SLEW_RATE_CLK = 0x1049,
+    SET_SI_MC_RCV_IMP_ALERT_N = 0x1050,
+    SET_SI_DRAM_RTT_NOM = 0x1051,
+    SET_SI_DRAM_RTT_WR = 0x1052,
+    SET_SI_DRAM_RTT_PARK = 0x1053,
+    SET_SI_DRAM_PREAMBLE = 0x1054,
+    SET_SI_MC_DRV_EQ_DQ_DQS = 0x1055,
+    SET_SI_DRAM_DRV_IMP_DQ_DQS = 0x1056,
+    SET_SI_VREF_DQ_TRAIN_RANGE = 0x1057,
+    SET_SI_VREF_DQ_TRAIN_VALUE = 0x1058,
+    SET_SI_ODT_WR = 0x1059,
+    SET_SI_ODT_RD = 0x1060,
+    SET_SI_GEARDOWN_MODE = 0x1061,
+    PRE_DATA_ENGINE_CTOR = 0x1062
 };
 
 ///