Revert PLL unlock commits of 45102 and 46563

Change-Id: I27f7c75d73881a54152a77c7ab2c8b49be19adb7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47148
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47162
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C

@@ -246,9 +246,6 @@ p9_hcd_cache_dpll_setup(
 
         FAPI_DBG("Clear PLL unlock errors in PCB slave, unmask FIR propagation");
         FAPI_TRY(putScom(i_target, EQ_ERROR_REG, 0xFFFFFFFFFFFFFFFF));
-        FAPI_TRY(getScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64));
-        l_data64.clearBit<12>();
-        FAPI_TRY(putScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64));
     }
 
     FAPI_DBG("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]");

src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H

@@ -528,17 +528,6 @@ p9_common_poweronoff(
     FAPI_DBG("Assert vital thold via NET_CTRL0[16]");
     FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(16)));
 
-    if (l_type == 1)
-    {
-        // upon power off cache, dpll is about to be unlocked
-        // to prevent pcb fir fires, need to mask the bit for the time being
-        // the error will be cleared and unmasked when dpll is locked again
-        FAPI_DBG("Mask DPLL unlock error in FIR via SLAVE_CONFIG[12]");
-        FAPI_TRY(getScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64));
-        l_data64.setBit<12>();
-        FAPI_TRY(putScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64));//
-    }
-
     ///////////////////////////////////////////////////////////////////////////
     // Procedure code
     ///////////////////////////////////////////////////////////////////////////

src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C

@@ -259,25 +259,21 @@ fapi2::ReturnCode p9_sbe_npll_setup(const
                                 l_data64_perv_ctrl0));
     }
 
+    // Clear Perv pcb slave error register
+    FAPI_DBG(" Reset PCB error reg");
     l_read_reg.flush<1>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_ERROR_REG, l_read_reg));
 
-    // Clear Perv pcb slave error register
     // Clearing mask bit in pcb slave config register [bit 12] to allow unlock error
     // to propagate to Pervasive Lfir [ bit 21]
     if (  l_nest_bypass == 0x0 &&  l_attr_cp_filter == 0x0 && l_attr_ss_filter == 0x0 && l_attr_io_filter == 0x0 )
     {
-
-        FAPI_DBG(" Reset PCB error reg");
-        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_ERROR_REG, l_read_reg));
-
         FAPI_DBG(" Unmasking pll unlock error in   Pcb slave config reg");
         FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_SLAVE_CONFIG_REG, l_read_reg));
         l_read_reg.clearBit<12>();
         FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_SLAVE_CONFIG_REG, l_read_reg));
     }
 
-
-
     FAPI_INF("p9_sbe_npll_setup: Exiting ...");
 
 fapi_try_exit: