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Change-Id: I8cb5e51ea84e59496fdf85fb5c815c3378045f5e
Original-Change-Id: I8159352751dd039f44e851315bf2b9d4cb1ab5fb
Cange-Id: I2b728046ef7b898666d3f1f0076e387f2d937f5b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32173
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48010
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Ashish authored and sgupta2m committed Oct 5, 2017
1 parent fcf4e20 commit 868a208
Showing 1 changed file with 65 additions and 142 deletions.
207 changes: 65 additions & 142 deletions src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C
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Original file line number Diff line number Diff line change
Expand Up @@ -45,151 +45,41 @@
#include <p9_hcd_common.H>
#include <map>

/**
* @brief enumerates opcodes for few instructions.
*/
enum
{
OPCODE_31 = 31,
MTSPR_CONST1 = 467,
MTSPR_BASE_OPCODE = (OPCODE_31 << (31 - 5)) | (MTSPR_CONST1 << (31 - 30)),
MFSPR_CONST1 = 339,
MFSPR_BASE_OPCODE = (OPCODE_31 << (31 - 5)) | (MFSPR_CONST1 << (31 - 30)),
MFMSRD_CONST1 = 83,
MFCR_CONST1 = 19,
ANDIS_CONST = 29,
ORIS_CONST = 25,
};


// Vector defining the special acceess egisters
std::vector<uint16_t> v_ppe_special_regs =
{
{ MSR },
{ CR },
};
// Vector defining the other xsr regs
std::vector<uint16_t> v_ppe_xsr_regs =
{
{ XSR },
{ IAR },
{ IR },
{ EDR },
{ SPRG0 },


};

// Vector defining the major SPRs
// Note: SPRG0 is not include as it is saved and restored as the means for
// accessing the other SPRS
std::vector<uint16_t> v_ppe_major_sprs =
{
{ CTR },
{ LR },
{ ISR },
{ SRR0 },
{ SRR1 },
{ TCR },
{ TSR },
};

// Vector defining the minor SPRs
std::vector<uint16_t> v_ppe_minor_sprs =
{
{ DACR },
{ DBCR },
{ DEC },
{ IVPR },
{ PIR },
{ PVR },
{ XER },
};

// Vector defining the GPRs
std::vector<uint16_t> v_ppe_gprs =
{
{ R0 },
{ R1 },
{ R2 },
{ R3 },
{ R4 },
{ R5 },
{ R6 },
{ R7 },
{ R8 },
{ R9 },
{ R10},
{ R13},
{ R28},
{ R29},
{ R30},
{ R31},
};


// Vector defining the special acceess egisters
const std::map<uint16_t, std::string> v_ppe_special_num_name =
{
{ MSR, "MSR" },
{ CR, "CR" }
};
// Vector defining the other xsr regs
const std::map<uint16_t, std::string> v_ppe_xsr_num_name =
{
{ XSR, "XSR" },
{ IAR, "IAR" },
{ IR, "IR" },
{ EDR, "EDR" },
{ SPRG0, "SPRG0" }
};

// Vector defining the major SPRs
// Note: SPRG0 is not include as it is saved and restored as the means for
// accessing the other SPRS
const std::map<uint16_t, std::string> v_ppe_major_num_name =
{
{ CTR, "CTR" },
{ LR, "LR" },
{ ISR, "ISR" },
{ SRR0, "SRR0" },
{ SRR1, "SRR1" },
{ TCR, "TCR" },
{ TSR, "TSR" }
};

// Vector defining the minor SPRs
const std::map<uint16_t, std::string> v_ppe_minor_num_name =
{
{ DACR, "DACR" },
{ DBCR, "DBCR" },
{ DEC, "DEC" },
{ IVPR, "IVPR" },
{ PIR, "PIR" },
{ PVR, "PVR" },
{ XER, "XER" }
};

// Vector defining the GPRs
const std::map<uint16_t, std::string> v_ppe_gprs_num_name =
{
{ R0, "R0" },
{ R1, "R1" },
{ R2, "R2" },
{ R3, "R3" },
{ R4, "R4" },
{ R5, "R5" },
{ R6, "R6" },
{ R7, "R7" },
{ R8, "R8" },
{ R9, "R9" },
{ R10, "R10" },
{ R13, "R13" },
{ R28, "R28" },
{ R29, "R29" },
{ R30, "R30" },
{ R31, "R31" }
};

//// Vector defining the special acceess egisters
//const std::map<uint16_t, std::string> v_ppe_special_num_name =
//{
// { MSR, "MSR" },
// { CR, "CR" }
//};
//// Vector defining the major SPRs
//// Note: SPRG0 is not include as it is saved and restored as the means for
//// accessing the other SPRS
//const std::map<uint16_t, std::string> v_ppe_major_num_name =
//{
// { CTR, "CTR" },
// { LR, "LR" },
// { ISR, "ISR" },
// { SRR0, "SRR0" },
// { SRR1, "SRR1" },
// { TCR, "TCR" },
// { TSR, "TSR" }
//};
//// Vector defining the minor SPRs
//const std::map<uint16_t, std::string> v_ppe_minor_num_name =
//{
// { DACR, "DACR" },
// { DBCR, "DBCR" },
// { DEC, "DEC" },
// { IVPR, "IVPR" },
// { PIR, "PIR" },
// { PVR, "PVR" },
// { XER, "XER" }
//};



//-----------------------------------------------------------------------------
Expand Down Expand Up @@ -836,3 +726,36 @@ fapi2::ReturnCode ppe_write_iar(
fapi_try_exit:
return fapi2::current_err;
}

//-----------------------------------------------------------------------------

/**
* @brief single step the engine
* @param[in] i_target target register number
* @return fapi2::ReturnCode
* @note output is l_scom_regs.] which has reg name added along with value and number
* this will be used for printing in the wrapper
*/
fapi2::ReturnCode scom_regs_populate_name(
std::vector<SCOMRegValue_t> l_ppe_regs_value,
const std::map<uint16_t, std::string> l_ppe_regs_num_name,
std::vector<SCOMReg_t>& l_scom_regs)

{
SCOMReg_t l_reg;
FAPI_INF(" populating reg names");

if (!l_ppe_regs_value.empty())
{
for (auto it : l_ppe_regs_value)
{
auto search = l_ppe_regs_num_name.find(it.number);
l_reg.name = search->second;
l_reg.reg = it;
l_scom_regs.push_back(l_reg);
}
}


return fapi2::current_err;
}

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