resolve Zeppelin DMI channel framelock issues

p9_sbe_chiplet_reset p9c_mc_scom resolve HW CQ 418671 set MC CPLT_CONF1 FASTX2 ratio controls in p9_sbe_chiplet_reset need to set prior to MC chiplet clock start for proper functional operation remove from initfile p9_cen_framelock resolve HW CQ 418901 analyze captured FRTL value along with FRTL counter overflow error FIR centaur.mcs.scan.initfile cen_scominits enable MBI trace array prior to framelock, to make usable for future debug Update p9c.mc.initfile to include fix for ZCAL to help with conflicts - bgass Change-Id: I7897d41250b9c113adf22fe40a8ca5971bca2a6f CQ: HW418671 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44708 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: LENNARD G. STREAT <lstreat@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
open-power · Sep 12, 2017 · 97617be · 97617be
1 parent b6fa4d1
commit 97617be
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diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -221,6 +221,10 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
         fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) //Skip for cache contained.
     {
 #endif
+        uint8_t l_is_p9c;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9C_LOGIC_ONLY,
+                               i_target_chip,
+                               l_is_p9c));
 
         // NEST OBUS XBUS PCI MC - Functional
         for (auto& targ : l_perv_func_WO_Core_Cache)
@@ -481,6 +485,20 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
             }
         }
 
+        for (auto& targ : l_perv_func)
+        {
+            //MC
+            uint32_t l_chipletID = targ.getChipletNumber();
+
+            if (l_is_p9c && (l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID))
+            {
+                FAPI_DBG("Set TC_IOM_FASTX2_RATIO_DC");
+                FAPI_TRY(fapi2::putScom(targ,
+                                        PERV_CPLT_CONF1_OR,
+                                        p9SbeChipletReset::MC_CPLT_CONF1_FASTX2_RATIO_MASK));
+            }
+        }
+
 #ifndef __PPE__
     }
 

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
@@ -91,7 +91,8 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants
     SIM_CYCLE_DELAY = 10000, // unit is cycles
     HANG_PULSE_0X12 = 0x12,
     HANG_PULSE_0X1C = 0x1C,
-    HANG_PULSE_0X08 = 0x08
+    HANG_PULSE_0X08 = 0x08,
+    MC_CPLT_CONF1_FASTX2_RATIO_MASK = 0x0000C00000000000ULL
 };
 }
 

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -4524,6 +4524,24 @@
     </chipEcFeature>
   </attribute>
 
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW418091</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Adjust FRTL latency overflow check for HW418091
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CUMULUS</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW355538</id>