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update i2c bit rate divisor for p9a
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p9a i2cm HW changes require nest/4/2/4 programming

Change-Id: Ib29c307fa2250f5096578809e3d0cb10a027086e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78640
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78664
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
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jjmcgill authored and RAJA DAS committed Jun 15, 2019
1 parent e99d1c0 commit c966910
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Showing 3 changed files with 29 additions and 2 deletions.
Expand Up @@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
Expand Down Expand Up @@ -58,6 +58,7 @@ fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
{
uint8_t l_attr_nest_pll_bucket = 0;
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
fapi2::ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2_Type l_i2cm_internal_clk_div2 = 0;
fapi2::buffer<uint16_t> l_mb_bit_rate_divisor;
fapi2::buffer<uint64_t> l_data64;

Expand All @@ -68,7 +69,11 @@ fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
l_attr_nest_pll_bucket));
FAPI_DBG("ATTR_NEST_PLL_BUCKET value: %d", l_attr_nest_pll_bucket);

l_mb_bit_rate_divisor = NEST_PLL_FREQ_I2CDIV_LIST[l_attr_nest_pll_bucket - 1];
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2, i_target_chip, l_i2cm_internal_clk_div2));

l_mb_bit_rate_divisor = NEST_PLL_FREQ_I2CDIV_LIST[l_attr_nest_pll_bucket - 1] *
((l_i2cm_internal_clk_div2) ? (2) : (1));

FAPI_DBG("bit_rate_divisor value: %d", l_mb_bit_rate_divisor);

FAPI_DBG("Adjust I2C bit rate divisor setting in I2CM B Mode Reg");
Expand Down
Expand Up @@ -132,6 +132,23 @@
</chipEcFeature>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
I2CM internal clock divider is div2 , not div4
</description>
<chipEcFeature>
<chip>
<name>ENUM_ATTR_NAME_AXONE</name>
<ec>
<value>0x10</value>
<test>GREATER_THAN_OR_EQUAL</test>
</ec>
</chip>
</chipEcFeature>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_NOT_DD1_FBC_AND_ALINK</id>
<targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType>
Expand Down
Expand Up @@ -628,4 +628,9 @@ attribute tank
<name>ATTR_LPC_CONSOLE_CNFG</name>
<value>0x00</value>
</entry>
<entry>
<name>ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2</name>
<virtual/>
</entry>

</entries>

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