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p7ioc-phb.c
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p7ioc-phb.c
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/* Copyright 2013-2014 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <skiboot.h>
#include <p7ioc.h>
#include <p7ioc-regs.h>
#include <io.h>
#include <timebase.h>
#include <affinity.h>
#include <pci-cfg.h>
#include <pci.h>
#include <pci-slot.h>
#include <interrupts.h>
#include <opal.h>
#include <ccan/str/str.h>
#define PHBDBG(p, fmt, a...) prlog(PR_DEBUG, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
#define PHBERR(p, fmt, a...) prlog(PR_ERR, "PHB#%04x: " fmt, \
(p)->phb.opal_id, ## a)
/* Helper to select an IODA table entry */
static inline void p7ioc_phb_ioda_sel(struct p7ioc_phb *p, uint32_t table,
uint32_t addr, bool autoinc)
{
out_be64(p->regs + PHB_IODA_ADDR,
(autoinc ? PHB_IODA_AD_AUTOINC : 0) |
SETFIELD(PHB_IODA_AD_TSEL, 0ul, table) |
SETFIELD(PHB_IODA_AD_TADR, 0ul, addr));
}
static bool p7ioc_phb_fenced(struct p7ioc_phb *p)
{
struct p7ioc *ioc = p->ioc;
uint64_t fence, fbits;
fbits = 0x0003000000000000UL >> (p->index * 4);
fence = in_be64(ioc->regs + P7IOC_CHIP_FENCE_SHADOW);
return (fence & fbits) != 0;
}
/*
* Configuration space access
*
* The PHB lock is assumed to be already held
*/
static int64_t p7ioc_pcicfg_check(struct p7ioc_phb *p, uint32_t bdfn,
uint32_t offset, uint32_t size)
{
uint32_t sm = size - 1;
if (offset > 0xfff || bdfn > 0xffff)
return OPAL_PARAMETER;
if (offset & sm)
return OPAL_PARAMETER;
/* The root bus only has a device at 0 and we get into an
* error state if we try to probe beyond that, so let's
* avoid that and just return an error to Linux
*/
if ((bdfn >> 8) == 0 && (bdfn & 0xff))
return OPAL_HARDWARE;
/* Check PHB state */
if (p->state == P7IOC_PHB_STATE_BROKEN)
return OPAL_HARDWARE;
return OPAL_SUCCESS;
}
#define P7IOC_PCI_CFG_READ(size, type) \
static int64_t p7ioc_pcicfg_read##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type *data) \
{ \
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb); \
uint64_t addr; \
void *base = p->regs; \
int64_t rc; \
\
/* Initialize data in case of error */ \
*data = (type)0xffffffff; \
\
rc = p7ioc_pcicfg_check(p, bdfn, offset, sizeof(type)); \
if (rc) \
return rc; \
\
if (p7ioc_phb_fenced(p)) { \
if (!(p->flags & P7IOC_PHB_CFG_USE_ASB)) \
return OPAL_HARDWARE; \
\
base = p->regs_asb; \
} else if ((p->flags & P7IOC_PHB_CFG_BLOCKED) && bdfn != 0) { \
return OPAL_HARDWARE; \
} \
\
addr = PHB_CA_ENABLE; \
addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \
addr = SETFIELD(PHB_CA_REG, addr, offset); \
out_be64(base + PHB_CONFIG_ADDRESS, addr); \
*data = in_le##size(base + PHB_CONFIG_DATA + \
(offset & (4 - sizeof(type)))); \
\
return OPAL_SUCCESS; \
}
#define P7IOC_PCI_CFG_WRITE(size, type) \
static int64_t p7ioc_pcicfg_write##size(struct phb *phb, uint32_t bdfn, \
uint32_t offset, type data) \
{ \
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb); \
void *base = p->regs; \
uint64_t addr; \
int64_t rc; \
\
rc = p7ioc_pcicfg_check(p, bdfn, offset, sizeof(type)); \
if (rc) \
return rc; \
\
if (p7ioc_phb_fenced(p)) { \
if (!(p->flags & P7IOC_PHB_CFG_USE_ASB)) \
return OPAL_HARDWARE; \
\
base = p->regs_asb; \
} else if ((p->flags & P7IOC_PHB_CFG_BLOCKED) && bdfn != 0) { \
return OPAL_HARDWARE; \
} \
\
addr = PHB_CA_ENABLE; \
addr = SETFIELD(PHB_CA_BDFN, addr, bdfn); \
addr = SETFIELD(PHB_CA_REG, addr, offset); \
out_be64(base + PHB_CONFIG_ADDRESS, addr); \
out_le##size(base + PHB_CONFIG_DATA + \
(offset & (4 - sizeof(type))), data); \
\
return OPAL_SUCCESS; \
}
P7IOC_PCI_CFG_READ(8, uint8_t)
P7IOC_PCI_CFG_READ(16, uint16_t)
P7IOC_PCI_CFG_READ(32, uint32_t)
P7IOC_PCI_CFG_WRITE(8, uint8_t)
P7IOC_PCI_CFG_WRITE(16, uint16_t)
P7IOC_PCI_CFG_WRITE(32, uint32_t)
static void p7ioc_eeh_read_phb_status(struct p7ioc_phb *p,
struct OpalIoP7IOCPhbErrorData *stat)
{
uint16_t tmp16;
unsigned int i;
memset(stat, 0, sizeof(struct OpalIoP7IOCPhbErrorData));
/* Error data common part */
stat->common.version = OPAL_PHB_ERROR_DATA_VERSION_1;
stat->common.ioType = OPAL_PHB_ERROR_DATA_TYPE_P7IOC;
stat->common.len = sizeof(struct OpalIoP7IOCPhbErrorData);
/*
* We read some registers using config space through AIB.
*
* Get to other registers using ASB when possible to get to them
* through a fence if one is present.
*
* Note that the OpalIoP7IOCPhbErrorData has oddities, such as the
* bridge control being 32-bit and the UTL registers being 32-bit
* (which they really are, but they use the top 32-bit of a 64-bit
* register so we need to be a bit careful).
*/
/* Use ASB to access PCICFG if the PHB has been fenced */
p->flags |= P7IOC_PHB_CFG_USE_ASB;
/* Grab RC bridge control, make it 32-bit */
p7ioc_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &tmp16);
stat->brdgCtl = tmp16;
/* Grab UTL status registers */
stat->portStatusReg = hi32(in_be64(p->regs_asb
+ UTL_PCIE_PORT_STATUS));
stat->rootCmplxStatus = hi32(in_be64(p->regs_asb
+ UTL_RC_STATUS));
stat->busAgentStatus = hi32(in_be64(p->regs_asb
+ UTL_SYS_BUS_AGENT_STATUS));
/*
* Grab various RC PCIe capability registers. All device, slot
* and link status are 16-bit, so we grab the pair control+status
* for each of them
*/
p7ioc_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL,
&stat->deviceStatus);
p7ioc_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL,
&stat->slotStatus);
p7ioc_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL,
&stat->linkStatus);
/*
* I assume those are the standard config space header, cmd & status
* together makes 32-bit. Secondary status is 16-bit so I'll clear
* the top on that one
*/
p7ioc_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus);
p7ioc_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &tmp16);
stat->devSecStatus = tmp16;
/* Grab a bunch of AER regs */
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA,
&stat->rootErrorStatus);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS,
&stat->uncorrErrorStatus);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS,
&stat->corrErrorStatus);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0,
&stat->tlpHdr1);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1,
&stat->tlpHdr2);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2,
&stat->tlpHdr3);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3,
&stat->tlpHdr4);
p7ioc_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID,
&stat->sourceId);
/* Restore to AIB */
p->flags &= ~P7IOC_PHB_CFG_USE_ASB;
/*
* No idea what that that is supposed to be, opal.h says
* "Record data about the call to allocate a buffer."
*
* Let's leave them alone for now...
*
* uint64_t errorClass;
* uint64_t correlator;
*/
/* P7IOC MMIO Error Regs */
stat->p7iocPlssr = in_be64(p->regs_asb + PHB_CPU_LOADSTORE_STATUS);
stat->p7iocCsr = in_be64(p->regs_asb + PHB_DMA_CHAN_STATUS);
stat->lemFir = in_be64(p->regs_asb + PHB_LEM_FIR_ACCUM);
stat->lemErrorMask = in_be64(p->regs_asb + PHB_LEM_ERROR_MASK);
stat->lemWOF = in_be64(p->regs_asb + PHB_LEM_WOF);
stat->phbErrorStatus = in_be64(p->regs_asb + PHB_ERR_STATUS);
stat->phbFirstErrorStatus = in_be64(p->regs_asb + PHB_ERR1_STATUS);
stat->phbErrorLog0 = in_be64(p->regs_asb + PHB_ERR_LOG_0);
stat->phbErrorLog1 = in_be64(p->regs_asb + PHB_ERR_LOG_1);
stat->mmioErrorStatus = in_be64(p->regs_asb + PHB_OUT_ERR_STATUS);
stat->mmioFirstErrorStatus = in_be64(p->regs_asb + PHB_OUT_ERR1_STATUS);
stat->mmioErrorLog0 = in_be64(p->regs_asb + PHB_OUT_ERR_LOG_0);
stat->mmioErrorLog1 = in_be64(p->regs_asb + PHB_OUT_ERR_LOG_1);
stat->dma0ErrorStatus = in_be64(p->regs_asb + PHB_INA_ERR_STATUS);
stat->dma0FirstErrorStatus = in_be64(p->regs_asb + PHB_INA_ERR1_STATUS);
stat->dma0ErrorLog0 = in_be64(p->regs_asb + PHB_INA_ERR_LOG_0);
stat->dma0ErrorLog1 = in_be64(p->regs_asb + PHB_INA_ERR_LOG_1);
stat->dma1ErrorStatus = in_be64(p->regs_asb + PHB_INB_ERR_STATUS);
stat->dma1FirstErrorStatus = in_be64(p->regs_asb + PHB_INB_ERR1_STATUS);
stat->dma1ErrorLog0 = in_be64(p->regs_asb + PHB_INB_ERR_LOG_0);
stat->dma1ErrorLog1 = in_be64(p->regs_asb + PHB_INB_ERR_LOG_1);
/* Grab PESTA & B content */
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTA, 0, true);
for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++)
stat->pestA[i] = in_be64(p->regs_asb + PHB_IODA_DATA0);
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTB, 0, true);
for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++)
stat->pestB[i] = in_be64(p->regs_asb + PHB_IODA_DATA0);
}
static int64_t p7ioc_eeh_freeze_status(struct phb *phb, uint64_t pe_number,
uint8_t *freeze_state,
uint16_t *pci_error_type,
uint16_t *severity,
uint64_t *phb_status)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
uint64_t peev_bit = PPC_BIT(pe_number & 0x3f);
uint64_t peev, pesta, pestb;
/* Defaults: not frozen */
*freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN;
*pci_error_type = OPAL_EEH_NO_ERROR;
/* Check dead */
if (p->state == P7IOC_PHB_STATE_BROKEN) {
*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
*pci_error_type = OPAL_EEH_PHB_ERROR;
if (severity)
*severity = OPAL_EEH_SEV_PHB_DEAD;
goto bail;
}
/* Check fence */
if (p7ioc_phb_fenced(p)) {
/* Should be OPAL_EEH_STOPPED_TEMP_UNAVAIL ? */
*freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE;
*pci_error_type = OPAL_EEH_PHB_ERROR;
if (severity)
*severity = OPAL_EEH_SEV_PHB_FENCED;
p->state = P7IOC_PHB_STATE_FENCED;
goto bail;
}
/* Check the PEEV */
p7ioc_phb_ioda_sel(p, IODA_TBL_PEEV, 0, true);
peev = in_be64(p->regs + PHB_IODA_DATA0);
if (pe_number > 63)
peev = in_be64(p->regs + PHB_IODA_DATA0);
if (!(peev & peev_bit))
return OPAL_SUCCESS;
/* Indicate that we have an ER pending */
p7ioc_phb_set_err_pending(p, true);
if (severity)
*severity = OPAL_EEH_SEV_PE_ER;
/* Read the PESTA & PESTB */
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTA, pe_number, false);
pesta = in_be64(p->regs + PHB_IODA_DATA0);
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTB, pe_number, false);
pestb = in_be64(p->regs + PHB_IODA_DATA0);
/* Convert them */
if (pesta & IODA_PESTA_MMIO_FROZEN)
*freeze_state |= OPAL_EEH_STOPPED_MMIO_FREEZE;
if (pestb & IODA_PESTB_DMA_STOPPED)
*freeze_state |= OPAL_EEH_STOPPED_DMA_FREEZE;
/* XXX Handle more causes */
if (pesta & IODA_PESTA_MMIO_CAUSE)
*pci_error_type = OPAL_EEH_PE_MMIO_ERROR;
else
*pci_error_type = OPAL_EEH_PE_DMA_ERROR;
bail:
if (phb_status)
p7ioc_eeh_read_phb_status(p, (struct OpalIoP7IOCPhbErrorData *)
phb_status);
return OPAL_SUCCESS;
}
static int64_t p7ioc_eeh_next_error(struct phb *phb, uint64_t *first_frozen_pe,
uint16_t *pci_error_type, uint16_t *severity)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
struct p7ioc *ioc = p->ioc;
uint64_t fir, peev0, peev1;
uint32_t cfg32, i;
/* Check if there're pending errors on the IOC. */
if (p7ioc_err_pending(ioc) &&
p7ioc_check_LEM(ioc, pci_error_type, severity))
return OPAL_SUCCESS;
/* Clear result */
*pci_error_type = OPAL_EEH_NO_ERROR;
*severity = OPAL_EEH_SEV_NO_ERROR;
*first_frozen_pe = (uint64_t)-1;
/* Check dead */
if (p->state == P7IOC_PHB_STATE_BROKEN) {
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_DEAD;
return OPAL_SUCCESS;
}
/* Check fence */
if (p7ioc_phb_fenced(p)) {
/* Should be OPAL_EEH_STOPPED_TEMP_UNAVAIL ? */
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_FENCED;
p->state = P7IOC_PHB_STATE_FENCED;
p7ioc_phb_set_err_pending(p, false);
return OPAL_SUCCESS;
}
/*
* If we don't have pending errors, which might be moved
* from IOC to the PHB, then check if there has any frozen PEs.
*/
if (!p7ioc_phb_err_pending(p)) {
p7ioc_phb_ioda_sel(p, IODA_TBL_PEEV, 0, true);
peev0 = in_be64(p->regs + PHB_IODA_DATA0);
peev1 = in_be64(p->regs + PHB_IODA_DATA0);
if (peev0 || peev1) {
p->err.err_src = P7IOC_ERR_SRC_PHB0 + p->index;
p->err.err_class = P7IOC_ERR_CLASS_ER;
p->err.err_bit = 0;
p7ioc_phb_set_err_pending(p, true);
}
}
/* Check the pending errors, which might come from IOC */
if (p7ioc_phb_err_pending(p)) {
/*
* If the frozen PE is caused by a malfunctioning TLP, we
* need reset the PHB. So convert ER to PHB-fatal error
* for the case.
*/
if (p->err.err_class == P7IOC_ERR_CLASS_ER) {
fir = in_be64(p->regs_asb + PHB_LEM_FIR_ACCUM);
if (fir & PPC_BIT(60)) {
p7ioc_pcicfg_read32(&p->phb, 0,
p->aercap + PCIECAP_AER_UE_STATUS, &cfg32);
if (cfg32 & PCIECAP_AER_UE_MALFORMED_TLP)
p->err.err_class = P7IOC_ERR_CLASS_PHB;
}
}
/*
* Map P7IOC internal error class to that one OS can handle.
* For P7IOC_ERR_CLASS_ER, we also need figure out the frozen
* PE.
*/
switch (p->err.err_class) {
case P7IOC_ERR_CLASS_PHB:
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_PHB_FENCED;
p7ioc_phb_set_err_pending(p, false);
break;
case P7IOC_ERR_CLASS_MAL:
case P7IOC_ERR_CLASS_INF:
*pci_error_type = OPAL_EEH_PHB_ERROR;
*severity = OPAL_EEH_SEV_INF;
p7ioc_phb_set_err_pending(p, false);
break;
case P7IOC_ERR_CLASS_ER:
*pci_error_type = OPAL_EEH_PE_ERROR;
*severity = OPAL_EEH_SEV_PE_ER;
p7ioc_phb_ioda_sel(p, IODA_TBL_PEEV, 0, true);
peev0 = in_be64(p->regs + PHB_IODA_DATA0);
peev1 = in_be64(p->regs + PHB_IODA_DATA0);
for (i = 0 ; i < 64; i++) {
if (PPC_BIT(i) & peev1) {
*first_frozen_pe = i + 64;
break;
}
}
for (i = 0 ;
*first_frozen_pe == (uint64_t)-1 && i < 64;
i++) {
if (PPC_BIT(i) & peev0) {
*first_frozen_pe = i;
break;
}
}
/* No frozen PE? */
if (*first_frozen_pe == (uint64_t)-1) {
*pci_error_type = OPAL_EEH_NO_ERROR;
*severity = OPAL_EEH_SEV_NO_ERROR;
p7ioc_phb_set_err_pending(p, false);
}
break;
default:
*pci_error_type = OPAL_EEH_NO_ERROR;
*severity = OPAL_EEH_SEV_NO_ERROR;
p7ioc_phb_set_err_pending(p, false);
}
}
return OPAL_SUCCESS;
}
static void p7ioc_ER_err_clear(struct p7ioc_phb *p)
{
u64 err, lem;
u32 val;
/* Rec 1,2 */
lem = in_be64(p->regs + PHB_LEM_FIR_ACCUM);
/* Rec 3,4,5 AER registers (could use cfg space accessors) */
out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000001c00000000ull);
out_be32(p->regs + PHB_CONFIG_DATA, 0x10000000);
/* Rec 6,7,8 XXX DOC whacks payload & req size ... we don't */
out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000005000000000ull);
val = in_be32(p->regs + PHB_CONFIG_DATA);
out_be32(p->regs + PHB_CONFIG_DATA, (val & 0xe0700000) | 0x0f000f00);
/* Rec 9,10,11 */
out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000010400000000ull);
out_be32(p->regs + PHB_CONFIG_DATA, 0xffffffff);
/* Rec 12,13,14 */
out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000011000000000ull);
out_be32(p->regs + PHB_CONFIG_DATA, 0xffffffff);
/* Rec 23,24,25 */
out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000013000000000ull);
out_be32(p->regs + PHB_CONFIG_DATA, 0xffffffff);
/* Rec 26,27,28 */
out_be64(p->regs + PHB_CONFIG_ADDRESS, 0x8000004000000000ull);
out_be32(p->regs + PHB_CONFIG_DATA, 0x470100f8);
/* Rec 29..34 UTL registers */
err = in_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS);
out_be64(p->regs + UTL_SYS_BUS_AGENT_STATUS, err);
err = in_be64(p->regs + UTL_PCIE_PORT_STATUS);
out_be64(p->regs + UTL_PCIE_PORT_STATUS, err);
err = in_be64(p->regs + UTL_RC_STATUS);
out_be64(p->regs + UTL_RC_STATUS, err);
/* PHB error traps registers */
err = in_be64(p->regs + PHB_ERR_STATUS);
out_be64(p->regs + PHB_ERR_STATUS, err);
out_be64(p->regs + PHB_ERR1_STATUS, 0);
out_be64(p->regs + PHB_ERR_LOG_0, 0);
out_be64(p->regs + PHB_ERR_LOG_1, 0);
err = in_be64(p->regs + PHB_OUT_ERR_STATUS);
out_be64(p->regs + PHB_OUT_ERR_STATUS, err);
out_be64(p->regs + PHB_OUT_ERR1_STATUS, 0);
out_be64(p->regs + PHB_OUT_ERR_LOG_0, 0);
out_be64(p->regs + PHB_OUT_ERR_LOG_1, 0);
err = in_be64(p->regs + PHB_INA_ERR_STATUS);
out_be64(p->regs + PHB_INA_ERR_STATUS, err);
out_be64(p->regs + PHB_INA_ERR1_STATUS, 0);
out_be64(p->regs + PHB_INA_ERR_LOG_0, 0);
out_be64(p->regs + PHB_INA_ERR_LOG_1, 0);
err = in_be64(p->regs + PHB_INB_ERR_STATUS);
out_be64(p->regs + PHB_INB_ERR_STATUS, err);
out_be64(p->regs + PHB_INB_ERR1_STATUS, 0);
out_be64(p->regs + PHB_INB_ERR_LOG_0, 0);
out_be64(p->regs + PHB_INB_ERR_LOG_1, 0);
/* Rec 67, 68 LEM */
out_be64(p->regs + PHB_LEM_FIR_AND_MASK, ~lem);
out_be64(p->regs + PHB_LEM_WOF, 0);
}
static int64_t p7ioc_eeh_freeze_clear(struct phb *phb, uint64_t pe_number,
uint64_t eeh_action_token)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
uint64_t peev0, peev1;
/* XXX Now this is a heavy hammer, coming roughly from the P7IOC doc
* and my old "pseudopal" code. It will need to be refined. In general
* error handling will have to be reviewed and probably done properly
* "from scratch" based on the description in the p7IOC spec.
*
* XXX Additionally, when handling interrupts, we might want to consider
* masking while processing and/or ack'ing interrupt bits etc...
*/
u64 err;
/* Summary. If nothing, move to clearing the PESTs which can
* contain a freeze state from a previous error or simply set
* explicitly by the user
*/
err = in_be64(p->regs + PHB_ETU_ERR_SUMMARY);
if (err == 0)
goto clear_pest;
p7ioc_ER_err_clear(p);
clear_pest:
/* XXX We just clear the whole PESTA for MMIO clear and PESTB
* for DMA clear. We might want to only clear the frozen bit
* as to not clobber the rest of the state. However, we expect
* the state to have been harvested before the clear operations
* so this might not be an issue
*/
if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO) {
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTA, pe_number, false);
out_be64(p->regs + PHB_IODA_DATA0, 0);
}
if (eeh_action_token & OPAL_EEH_ACTION_CLEAR_FREEZE_DMA) {
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTB, pe_number, false);
out_be64(p->regs + PHB_IODA_DATA0, 0);
}
/* Update ER pending indication */
p7ioc_phb_ioda_sel(p, IODA_TBL_PEEV, 0, true);
peev0 = in_be64(p->regs + PHB_IODA_DATA0);
peev1 = in_be64(p->regs + PHB_IODA_DATA0);
if (peev0 || peev1) {
p->err.err_src = P7IOC_ERR_SRC_PHB0 + p->index;
p->err.err_class = P7IOC_ERR_CLASS_ER;
p->err.err_bit = 0;
p7ioc_phb_set_err_pending(p, true);
} else
p7ioc_phb_set_err_pending(p, false);
return OPAL_SUCCESS;
}
static int64_t p7ioc_eeh_freeze_set(struct phb *phb, uint64_t pe_number,
uint64_t eeh_action_token)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
uint64_t data;
if (pe_number > 127)
return OPAL_PARAMETER;
if (eeh_action_token != OPAL_EEH_ACTION_SET_FREEZE_MMIO &&
eeh_action_token != OPAL_EEH_ACTION_SET_FREEZE_DMA &&
eeh_action_token != OPAL_EEH_ACTION_SET_FREEZE_ALL)
return OPAL_PARAMETER;
if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_MMIO) {
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTA, pe_number, false);
data = in_be64(p->regs + PHB_IODA_DATA0);
data |= IODA_PESTA_MMIO_FROZEN;
out_be64(p->regs + PHB_IODA_DATA0, data);
}
if (eeh_action_token & OPAL_EEH_ACTION_SET_FREEZE_DMA) {
p7ioc_phb_ioda_sel(p, IODA_TBL_PESTB, pe_number, false);
data = in_be64(p->regs + PHB_IODA_DATA0);
data |= IODA_PESTB_DMA_STOPPED;
out_be64(p->regs + PHB_IODA_DATA0, data);
}
return OPAL_SUCCESS;
}
static int64_t p7ioc_err_inject_finalize(struct p7ioc_phb *p, uint64_t addr,
uint64_t mask, uint64_t ctrl,
bool is_write)
{
if (is_write)
ctrl |= PHB_PAPR_ERR_INJ_CTL_WR;
else
ctrl |= PHB_PAPR_ERR_INJ_CTL_RD;
/* HW100549: Take read and write for outbound errors
* on DD10 chip
*/
if (p->rev == P7IOC_REV_DD10)
ctrl |= (PHB_PAPR_ERR_INJ_CTL_RD | PHB_PAPR_ERR_INJ_CTL_WR);
out_be64(p->regs + PHB_PAPR_ERR_INJ_ADDR, addr);
out_be64(p->regs + PHB_PAPR_ERR_INJ_MASK, mask);
out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, ctrl);
return OPAL_SUCCESS;
}
static int64_t p7ioc_err_inject_mem32(struct p7ioc_phb *p, uint64_t pe_number,
uint64_t addr, uint64_t mask,
bool is_write)
{
uint64_t a, m, prefer, base;
uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_OUTB;
int32_t index;
a = 0x0ull;
prefer = 0x0ull;
for (index = 0; index < 128; index++) {
if (GETFIELD(IODA_XXDT_PE, p->m32d_cache[index]) != pe_number)
continue;
base = p->m32_base + M32_PCI_START +
(M32_PCI_SIZE / 128) * index;
/* Update preferred address */
if (!prefer) {
prefer = GETFIELD(PHB_PAPR_ERR_INJ_MASK_MMIO, base);
prefer = SETFIELD(PHB_PAPR_ERR_INJ_MASK_MMIO,
0x0ull, prefer);
}
/* The input address matches ? */
if (addr >= base &&
addr < base + (M32_PCI_SIZE / 128)) {
a = addr;
break;
}
}
/* Invalid PE number */
if (!prefer)
return OPAL_PARAMETER;
/* Specified address is out of range */
if (!a) {
a = prefer;
m = PHB_PAPR_ERR_INJ_MASK_MMIO;
} else {
m = mask;
}
return p7ioc_err_inject_finalize(p, a, m, ctrl, is_write);
}
static int64_t p7ioc_err_inject_io32(struct p7ioc_phb *p, uint64_t pe_number,
uint64_t addr, uint64_t mask,
bool is_write)
{
uint64_t a, m, prefer, base;
uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_OUTB;
int32_t index;
a = 0x0ull;
prefer = 0x0ull;
for (index = 0; index < 128; index++) {
if (GETFIELD(IODA_XXDT_PE, p->iod_cache[index]) != pe_number)
continue;
base = p->io_base + (PHB_IO_SIZE / 128) * index;
/* Update preferred address */
if (!prefer) {
prefer = GETFIELD(PHB_PAPR_ERR_INJ_MASK_IO, base);
prefer = SETFIELD(PHB_PAPR_ERR_INJ_MASK_IO, 0x0ull, prefer);
}
/* The input address matches ? */
if (addr >= base &&
addr < base + (PHB_IO_SIZE / 128)) {
a = addr;
break;
}
}
/* Invalid PE number */
if (!prefer)
return OPAL_PARAMETER;
/* Specified address is out of range */
if (!a) {
a = prefer;
m = PHB_PAPR_ERR_INJ_MASK_IO;
} else {
m = mask;
}
return p7ioc_err_inject_finalize(p, a, m, ctrl, is_write);
}
static int64_t p7ioc_err_inject_cfg(struct p7ioc_phb *p, uint64_t pe_number,
uint64_t addr, uint64_t mask,
bool is_write)
{
uint64_t a, m;
uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_CFG;
uint8_t v_bits, base, bus_no;
/* Looking into PELTM to see if the PCI bus# is owned
* by the PE#. Otherwise, we have to figure one out.
*/
base = GETFIELD(IODA_PELTM_BUS, p->peltm_cache[pe_number]);
v_bits = GETFIELD(IODA_PELTM_BUS_VALID, p->peltm_cache[pe_number]);
switch (v_bits) {
case IODA_BUS_VALID_3_BITS:
case IODA_BUS_VALID_4_BITS:
case IODA_BUS_VALID_5_BITS:
case IODA_BUS_VALID_6_BITS:
case IODA_BUS_VALID_7_BITS:
case IODA_BUS_VALID_ALL:
base = GETFIELD(IODA_PELTM_BUS, p->peltm_cache[pe_number]);
base &= (0xff - (((1 << (7 - v_bits)) - 1)));
a = SETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, 0x0ul, base);
m = PHB_PAPR_ERR_INJ_MASK_CFG;
bus_no = GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr);
bus_no &= (0xff - (((1 << (7 - v_bits)) - 1)));
if (base == bus_no) {
a = addr;
m = mask;
}
break;
case IODA_BUS_VALID_ANY:
default:
return OPAL_PARAMETER;
}
return p7ioc_err_inject_finalize(p, a, m, ctrl, is_write);
}
static int64_t p7ioc_err_inject_dma(struct p7ioc_phb *p, uint64_t pe_number,
uint64_t addr, uint64_t mask,
bool is_write)
{
uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_INB;
int32_t index;
/* For DMA, we just pick address from TVT */
for (index = 0; index < 128; index++) {
if (GETFIELD(IODA_TVT1_PE_NUM, p->tve_hi_cache[index]) !=
pe_number)
continue;
addr = SETFIELD(PHB_PAPR_ERR_INJ_MASK_DMA, 0ul, index);
mask = PHB_PAPR_ERR_INJ_MASK_DMA;
break;
}
/* Some PE might not have DMA capability */
if (index >= 128)
return OPAL_PARAMETER;
return p7ioc_err_inject_finalize(p, addr, mask, ctrl, is_write);
}
static int64_t p7ioc_err_inject(struct phb *phb, uint64_t pe_number,
uint32_t type, uint32_t func,
uint64_t addr, uint64_t mask)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
int64_t (*handler)(struct p7ioc_phb *p, uint64_t pe_number,
uint64_t addr, uint64_t mask, bool is_write);
bool is_write;
/* To support 64-bits error later */
if (type == OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64)
return OPAL_UNSUPPORTED;
/* We can't inject error to the reserved PE#127 */
if (pe_number > 126)
return OPAL_PARAMETER;
/* Clear the leftover from last time */
out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
/* Check if PE number is valid one in PELTM cache */
if (p->peltm_cache[pe_number] == 0x0001f80000000000ull)
return OPAL_PARAMETER;
/* Clear the leftover from last time */
out_be64(p->regs + PHB_PAPR_ERR_INJ_CTL, 0x0ul);
switch (func) {
case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA:
is_write = false;
handler = p7ioc_err_inject_mem32;
break;
case OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA:
is_write = true;
handler = p7ioc_err_inject_mem32;
break;
case OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA:
is_write = false;
handler = p7ioc_err_inject_io32;
break;
case OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA:
is_write = true;
handler = p7ioc_err_inject_io32;
break;
case OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA:
is_write = false;
handler = p7ioc_err_inject_cfg;
break;
case OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA:
is_write = true;
handler = p7ioc_err_inject_cfg;
break;
case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA:
case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER:
case OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET:
is_write = false;
handler = p7ioc_err_inject_dma;
break;
case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR:
case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA:
case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER:
case OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET:
is_write = true;
handler = p7ioc_err_inject_dma;
break;
default:
return OPAL_PARAMETER;
}
return handler(p, pe_number, addr, mask, is_write);
}
static int64_t p7ioc_get_diag_data(struct phb *phb, void *diag_buffer,
uint64_t diag_buffer_len)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
struct OpalIoP7IOCPhbErrorData *diag = diag_buffer;
if (diag_buffer_len < sizeof(struct OpalIoP7IOCPhbErrorData))
return OPAL_PARAMETER;
/* Specific error data */
p7ioc_eeh_read_phb_status(p, diag);
/*
* We're running to here probably because of errors (MAL
* or INF class) from IOC. For the case, we need clear
* the pending errors and mask the error bit for MAL class
* error. Fortunately, we shouldn't get MAL class error from
* IOC on P7IOC.
*/
if (p7ioc_phb_err_pending(p) &&
p->err.err_class == P7IOC_ERR_CLASS_INF &&
p->err.err_src >= P7IOC_ERR_SRC_PHB0 &&
p->err.err_src <= P7IOC_ERR_SRC_PHB5) {
p7ioc_ER_err_clear(p);
p7ioc_phb_set_err_pending(p, false);
}
return OPAL_SUCCESS;
}
/*
* We don't support address remapping now since all M64
* BARs are sharing on remapping base address. We might
* introduce flag to the PHB in order to trace that. The
* flag allows to be changed for once. It's something to
* do in future.
*/
static int64_t p7ioc_set_phb_mem_window(struct phb *phb,
uint16_t window_type,
uint16_t window_num,
uint64_t base,
uint64_t __unused pci_base,
uint64_t size)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
uint64_t data64;
switch (window_type) {
case OPAL_IO_WINDOW_TYPE:
case OPAL_M32_WINDOW_TYPE:
return OPAL_UNSUPPORTED;
case OPAL_M64_WINDOW_TYPE:
if (window_num >= 16)
return OPAL_PARAMETER;
/* The base and size should be 16MB aligned */
if (base & 0xFFFFFF || size & 0xFFFFFF)
return OPAL_PARAMETER;
data64 = p->m64b_cache[window_num];
data64 = SETFIELD(IODA_M64BT_BASE, data64, base >> 24);
size = (size >> 24);
data64 = SETFIELD(IODA_M64BT_MASK, data64, 0x1000000 - size);
break;
default:
return OPAL_PARAMETER;
}
/*
* If the M64 BAR hasn't enabled yet, we needn't flush
* the setting to hardware and just keep it to the cache
*/
p->m64b_cache[window_num] = data64;
if (!(data64 & IODA_M64BT_ENABLE))
return OPAL_SUCCESS;
p7ioc_phb_ioda_sel(p, IODA_TBL_M64BT, window_num, false);
out_be64(p->regs + PHB_IODA_DATA0, data64);
return OPAL_SUCCESS;
}
/*
* We can't enable or disable I/O and M32 dynamically, even
* unnecessary. So the function only support M64 BARs.
*/
static int64_t p7ioc_phb_mmio_enable(struct phb *phb,
uint16_t window_type,
uint16_t window_num,
uint16_t enable)
{
struct p7ioc_phb *p = phb_to_p7ioc_phb(phb);
uint64_t data64, base, mask;
switch (window_type) {
case OPAL_IO_WINDOW_TYPE:
case OPAL_M32_WINDOW_TYPE:
return OPAL_UNSUPPORTED;
case OPAL_M64_WINDOW_TYPE:
if (window_num >= 16 ||
enable >= OPAL_ENABLE_M64_NON_SPLIT)
return OPAL_PARAMETER;
break;
default: