Remove POWER7 and POWER7+ support

It's been a good long while since either OPAL POWER7 user touched a
machine, and even longer since they'd have been okay using an old
version rather than tracking master.

There's also been no testing of OPAL on POWER7 systems for an awfully
long time, so it's pretty safe to assume that it's very much bitrotted.

It also saves a whole 14kb of xz compressed payload space.

Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

asm/head.S

@@ -44,12 +44,6 @@
 	. = 0
 .global __head
 __head:
-	/*
-	 * When booting a P7 machine in OPAL mode this pointer is used to
-	 * find the opal variant of the NACA. Unused on other machines.
-	 */
-	.llong	opal_naca
-
 	/* This entry point is used when booting with a flat device-tree
 	 * pointer in r3
 	 */
@@ -343,10 +337,6 @@ boot_entry:
 	mfspr	%r28,SPR_PVR
 	li	%r26,3	/* Default to SMT4 */
 	srdi	%r3,%r28,16
-	cmpwi	cr0,%r3,PVR_TYPE_P7
-	beq	1f
-	cmpwi	cr0,%r3,PVR_TYPE_P7P
-	beq	1f
 	cmpwi	cr0,%r3,PVR_TYPE_P8
 	beq	2f
 	cmpwi	cr0,%r3,PVR_TYPE_P8E
@@ -693,10 +683,6 @@ init_shared_sprs:
 
 	mfspr	%r3,SPR_PVR
 	srdi	%r3,%r3,16
-	cmpwi	cr0,%r3,PVR_TYPE_P7
-	beq	1f
-	cmpwi	cr0,%r3,PVR_TYPE_P7P
-	beq	2f
 	cmpwi	cr0,%r3,PVR_TYPE_P8E
 	beq	3f
 	cmpwi	cr0,%r3,PVR_TYPE_P8
@@ -710,20 +696,6 @@ init_shared_sprs:
 	/* Unsupported CPU type... what do we do ? */
 	b	9f
 
-1:	/* P7 */
-	mtspr	SPR_SDR1, %r0
-	/* TSCR: Value from pHyp */
-	LOAD_IMM32(%r3,0x880DE880)
-	mtspr	SPR_TSCR, %r3
-	b	9f
-
-2:	/* P7+ */
-	mtspr	SPR_SDR1, %r0
-	/* TSCR: Recommended value by HW folks */
-	LOAD_IMM32(%r3,0x88CDE880)
-	mtspr	SPR_TSCR, %r3
-	b	9f
-
 3:	/* P8E/P8 */
 	mtspr	SPR_SDR1, %r0
 	/* TSCR: Recommended value by HW folks */
@@ -795,10 +767,6 @@ init_shared_sprs:
 init_replicated_sprs:
 	mfspr	%r3,SPR_PVR
 	srdi	%r3,%r3,16
-	cmpwi	cr0,%r3,PVR_TYPE_P7
-	beq	1f
-	cmpwi	cr0,%r3,PVR_TYPE_P7P
-	beq	1f
 	cmpwi	cr0,%r3,PVR_TYPE_P8E
 	beq	3f
 	cmpwi	cr0,%r3,PVR_TYPE_P8
@@ -812,16 +780,6 @@ init_replicated_sprs:
 	/* Unsupported CPU type... what do we do ? */
 	b	9f
 
-1:	/* P7, P7+ */
-	/* LPCR: sane value */
-	LOAD_IMM64(%r3,0x0040000000000004)
-	mtspr	SPR_LPCR, %r3
-	sync
-	isync
-	LOAD_IMM64(%r3,0x0)
-	mtspr	SPR_DSCR,%r3
-	b	9f
-
 3:	/* P8, P8E */
 	/* LPCR: sane value */
 	LOAD_IMM64(%r3,0x0040000000000000)
@@ -903,22 +861,6 @@ hv_lid_load_table:
 	.long	0
 	.long	0
 
-/*
- *
- * OPAL variant of NACA. This is only used when booting a P7 in OPAL mode.
- *
- */
-.global opal_naca
-opal_naca:
-	.llong	opal_boot_trampoline	/* Primary entry (used ?) */
-	.llong	opal_boot_trampoline	/* Secondary entry (used ?) */
-	.llong	spira			/* Spira pointer */
-	.llong	0			/* Load address */
-	.llong	opal_boot_trampoline	/* 0x180 trampoline */
-	.llong	0			/* More stuff as seen in objdump ...*/
-	.llong	0
-	.llong	0
-	.llong	0
 
 	/* The FSP seems to ignore our primary/secondary entry
 	 * points and instead copy that bit down to 0x180 and

core/affinity.c

@@ -120,9 +120,7 @@ void add_core_associativity(struct cpu_thread *cpu)
 	if (!chip)
 		return;
 
-	if (proc_gen == proc_gen_p7)
-		core_id = (cpu->pir >> 2) & 0x7;
-	else if (proc_gen == proc_gen_p8)
+	if (proc_gen == proc_gen_p8)
 		core_id = (cpu->pir >> 3) & 0xf;
 	else if (proc_gen == proc_gen_p9)
 		core_id = (cpu->pir >> 2) & 0x1f;

core/chip.c

@@ -31,7 +31,7 @@ uint32_t pir_to_chip_id(uint32_t pir)
 	else if (proc_gen == proc_gen_p8)
 		return P8_PIR2GCID(pir);
 	else
-		return P7_PIR2GCID(pir);
+		assert(false);
 }
 
 uint32_t pir_to_core_id(uint32_t pir)
@@ -41,7 +41,7 @@ uint32_t pir_to_core_id(uint32_t pir)
 	else if (proc_gen == proc_gen_p8)
 		return P8_PIR2COREID(pir);
 	else
-		return P7_PIR2COREID(pir);
+		assert(false);
 }
 
 uint32_t pir_to_thread_id(uint32_t pir)
@@ -51,7 +51,7 @@ uint32_t pir_to_thread_id(uint32_t pir)
 	else if (proc_gen == proc_gen_p8)
 		return P8_PIR2THREADID(pir);
 	else
-		return P7_PIR2THREADID(pir);
+		assert(false);
 }
 
 struct proc_chip *next_chip(struct proc_chip *chip)

core/cpu.c

@@ -110,7 +110,7 @@ static void cpu_wake(struct cpu_thread *cpu)
 	if (!cpu->in_idle)
 		return;
 
-	if (proc_gen == proc_gen_p8 || proc_gen == proc_gen_p7) {
+	if (proc_gen == proc_gen_p8) {
 		/* Poke IPI */
 		icp_kick_cpu(cpu);
 	} else if (proc_gen == proc_gen_p9) {
@@ -992,10 +992,6 @@ void init_boot_cpu(void)
 
 	/* Get CPU family and other flags based on PVR */
 	switch(PVR_TYPE(pvr)) {
-	case PVR_TYPE_P7:
-	case PVR_TYPE_P7P:
-		proc_gen = proc_gen_p7;
-		break;
 	case PVR_TYPE_P8E:
 	case PVR_TYPE_P8:
 		proc_gen = proc_gen_p8;
@@ -1023,11 +1019,6 @@ void init_boot_cpu(void)
 
 	/* Get a CPU thread count based on family */
 	switch(proc_gen) {
-	case proc_gen_p7:
-		cpu_thread_count = 4;
-		prlog(PR_INFO, "CPU: P7 generation processor"
-		      " (max %d threads/core)\n", cpu_thread_count);
-		break;
 	case proc_gen_p8:
 		cpu_thread_count = 8;
 		prlog(PR_INFO, "CPU: P8 generation processor"
@@ -1580,13 +1571,6 @@ static int64_t opal_reinit_cpus(uint64_t flags)
 	if (req.set_bits || req.clr_bits)
 		cpu_change_all_hid0(&req);
 
-	/* If we have a P7, error out for LE switch, do nothing for BE */
-	if (proc_gen < proc_gen_p8) {
-		if (flags & OPAL_REINIT_CPUS_HILE_LE)
-			rc = OPAL_UNSUPPORTED;
-		flags &= ~(OPAL_REINIT_CPUS_HILE_BE | OPAL_REINIT_CPUS_HILE_LE);
-	}
-
 	if (flags & OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) {
 		flags &= ~OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED;
 

core/init.c

@@ -1103,9 +1103,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)
 	/* Allocate our split trace buffers now. Depends add_opal_node() */
 	init_trace_buffers();
 
-	/* On P7/P8, get the ICPs and make sure they are in a sane state */
+	/* On P8, get the ICPs and make sure they are in a sane state */
 	init_interrupts();
-	if (proc_gen == proc_gen_p7 || proc_gen == proc_gen_p8)
+	if (proc_gen == proc_gen_p8)
 		cpu_set_ipi_enable(true);
 
 	/* On P9, initialize XIVE */
@@ -1238,9 +1238,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)
 	/* Init In-Memory Collection related stuff (load the IMC dtb into memory) */
 	imc_init();
 
-	/* Probe IO hubs */
-	probe_p7ioc();
-
 	/* Probe PHB3 on P8 */
 	probe_phb3();
 

core/interrupts.c

@@ -152,16 +152,6 @@ uint32_t get_psi_interrupt(uint32_t chip_id)
 	uint32_t irq;
 
 	switch(proc_gen) {
-	case proc_gen_p7:
-		/* Get the chip ID into position, it already has
-		 * the T bit so all we need is room for the GX
-		 * bit, 9 bit BUID and 4 bit level
-		 */
-		irq  = chip_id << (1 + 9 + 4);
-
-		/* Add in the BUID */
-		irq |= P7_PSI_IRQ_BUID << 4;
-		break;
 	case proc_gen_p8:
 		irq = p8_chip_irq_block_base(chip_id, P8_IRQ_BLOCK_MISC);
 		irq += P8_IRQ_MISC_PSI_BASE;

core/test/run-cpufeatures.c

@@ -44,7 +44,7 @@ static inline unsigned long mfspr(unsigned int spr);
 
 #include "../cpufeatures.c"
 
-static unsigned long fake_pvr = PVR_TYPE_P7;
+static unsigned long fake_pvr = PVR_TYPE_P8;
 
 static inline unsigned long mfspr(unsigned int spr)
 {

core/test/run-flash-firmware-versions.c

@@ -103,7 +103,7 @@ char __rodata_start[1], __rodata_end[1];
 
 const char version[]="Hello world!";
 
-enum proc_gen proc_gen = proc_gen_p7;
+enum proc_gen proc_gen = proc_gen_p8;
 
 static char *loaded_version_buf;
 static size_t loaded_version_buf_size;

doc/opal-api/opal-pci-get-hub-diag-data-50.rst

@@ -7,61 +7,14 @@ OPAL_PCI_GET_HUB_DIAG_DATA
 
    #define OPAL_PCI_GET_HUB_DIAG_DATA		50
 
-   enum {
-	OPAL_P7IOC_DIAG_TYPE_NONE	= 0,
-	OPAL_P7IOC_DIAG_TYPE_RGC	= 1,
-	OPAL_P7IOC_DIAG_TYPE_BI		= 2,
-	OPAL_P7IOC_DIAG_TYPE_CI		= 3,
-	OPAL_P7IOC_DIAG_TYPE_MISC	= 4,
-	OPAL_P7IOC_DIAG_TYPE_I2C	= 5,
-	OPAL_P7IOC_DIAG_TYPE_LAST	= 6
-   };
-
-   struct OpalIoP7IOCErrorData {
-	__be16 type;
-
-	/* GEM */
-	__be64 gemXfir;
-	__be64 gemRfir;
-	__be64 gemRirqfir;
-	__be64 gemMask;
-	__be64 gemRwof;
-
-	/* LEM */
-	__be64 lemFir;
-	__be64 lemErrMask;
-	__be64 lemAction0;
-	__be64 lemAction1;
-	__be64 lemWof;
-
-	union {
-		struct OpalIoP7IOCRgcErrorData {
-			__be64 rgcStatus;	/* 3E1C10 */
-			__be64 rgcLdcp;		/* 3E1C18 */
-		}rgc;
-		struct OpalIoP7IOCBiErrorData {
-			__be64 biLdcp0;		/* 3C0100, 3C0118 */
-			__be64 biLdcp1;		/* 3C0108, 3C0120 */
-			__be64 biLdcp2;		/* 3C0110, 3C0128 */
-			__be64 biFenceStatus;	/* 3C0130, 3C0130 */
-
-			uint8_t biDownbound;	/* BI Downbound or Upbound */
-		}bi;
-		struct OpalIoP7IOCCiErrorData {
-			__be64 ciPortStatus;	/* 3Dn008 */
-			__be64 ciPortLdcp;	/* 3Dn010 */
-
-			uint8_t ciPort;		/* Index of CI port: 0/1 */
-		}ci;
-	};
-   };
-
    int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
 
-Fetch diagnostic data for an IO hub. Currently, this is only implemented for
-p7ioc, which is specific to POWER7, something that was only ever available
+Fetch diagnostic data for an IO hub. This was only implemented for hardware
+specific to POWER7 systems, something that was only ever available
 internally to IBM for development purposes.
 
+It is currently not used.
+
 If :ref:`OPAL_PCI_NEXT_ERROR` error type is `OPAL_EEH_IOC_ERROR` and severity
 is `OPAL_EEH_SEV_INF`, then the OS should call :ref:`OPAL_PCI_GET_HUB_DIAG_DATA`
 to retreive diagnostic data to log appropriately.

external/xscom-utils/adu_scoms.py

@@ -176,11 +176,7 @@ def chip_info(self, chip_id):
 
 		c_id = val >> 44
 		id = c_id & 0xff
-		if id == 0xf9:
-			name = "P7 processor"
-		elif id == 0xe8:
-			name = "P7+ processor"
-		elif id == 0xef:
+                if id == 0xef:
 			name = "P8E (Murano) processor"
 		elif id == 0xea:
 			name = "P8 (Venice) processor"

external/xscom-utils/getscom.c

@@ -47,12 +47,6 @@ static void print_chip_info(uint32_t chip_id)
 	cfam_id = f000f >> 44;
 
 	switch(cfam_id & 0xff) {
-	case 0xf9:
-		name = "P7 processor";
-		break;
-	case 0xe8:
-		name = "P7+ processor";
-		break;
 	case 0xef:
 		name = "P8E (Murano) processor";
 		break;
@@ -79,7 +73,6 @@ static void print_chip_info(uint32_t chip_id)
 
 	printf("%08x | DD%lx.%lx | %s\n",
 	       chip_id, (cfam_id >> 16) & 0xf, (cfam_id >> 8) & 0xf, name);
-
 }
 
 extern const char version[];

hdata/cpu-common.c

@@ -30,12 +30,6 @@ struct dt_node * add_core_common(struct dt_node *cpus,
 	struct dt_node *cpu;
 	uint32_t version;
 	uint64_t freq;
-	const uint8_t pa_features_p7[] = {
-		6, 0,
-		0xf6, 0x3f, 0xc7, 0x00, 0x80, 0xc0 };
-	const uint8_t pa_features_p7p[] = {
-		6, 0,
-		0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xc0 };
 	const uint8_t pa_features_p8[] = {
 	       24, 0,
 	       0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00,
@@ -80,16 +74,6 @@ struct dt_node * add_core_common(struct dt_node *cpus,
 	 */
 	version = mfspr(SPR_PVR);
 	switch(PVR_TYPE(version)) {
-	case PVR_TYPE_P7:
-		name = "PowerPC,POWER7";
-		pa_features = pa_features_p7;
-		pa_features_size = sizeof(pa_features_p7);
-		break;
-	case PVR_TYPE_P7P:
-		name = "PowerPC,POWER7+";
-		pa_features = pa_features_p7p;
-		pa_features_size = sizeof(pa_features_p7p);
-		break;
 	case PVR_TYPE_P8E:
 	case PVR_TYPE_P8:
 	case PVR_TYPE_P8NVL: