hw: Introduce npu3

POWER9P systems have been upgraded with NVLink 3.0 interconnects. The
underlying hardware is fundamentally different--each POWER9 chip has

        (1 NPU) * (3 stacks) * (2 bricks) = (6 links)

Where in each POWER9P chip, there are

        (3 NPUs) * (4 bricks) = (12 links)

This flatter hierarchy simplifies the firmware implementation a bit, but
also prevents sharing much common code with npu2.

As in previous versions, initialize the hardware and expose each link to
the OS as a virtual PCIe device. This initial support covers NVLink
devices only, with OpenCAPI to follow.

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>

core/init.c

@@ -1226,6 +1226,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)
 	/* Probe NPUs */
 	probe_npu();
 	probe_npu2();
+	probe_npu3();
 
 	/* Initialize PCI */
 	pci_init_slots();

hw/Makefile.inc

@@ -8,7 +8,7 @@ HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o
 HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o
 HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o
 HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o
-HW_OBJS += npu-opal.o
+HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o
 HW=hw/built-in.a
 
 include $(SRC)/hw/fsp/Makefile.inc

hw/npu-opal.c

@@ -18,16 +18,23 @@
 #include <pci.h>
 #include <phb4.h>
 #include <npu2.h>
+#include <npu3.h>
 
 static int64_t opal_npu_init_context(uint64_t phb_id, int pid __unused,
 				     uint64_t msr, uint64_t bdf)
 {
 	struct phb *phb = pci_get_phb(phb_id);
 
-	if (!phb || phb->phb_type != phb_type_npu_v2)
+	if (!phb)
 		return OPAL_PARAMETER;
 
-	return npu2_init_context(phb, msr, bdf);
+	if (phb->phb_type == phb_type_npu_v2)
+		return npu2_init_context(phb, msr, bdf);
+
+	if (phb->phb_type == phb_type_npu_v3)
+		return npu3_init_context(phb, msr, bdf);
+
+	return OPAL_PARAMETER;
 }
 opal_call(OPAL_NPU_INIT_CONTEXT, opal_npu_init_context, 4);
 
@@ -36,10 +43,16 @@ static int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid __unused,
 {
 	struct phb *phb = pci_get_phb(phb_id);
 
-	if (!phb || phb->phb_type != phb_type_npu_v2)
+	if (!phb)
 		return OPAL_PARAMETER;
 
-	return npu2_destroy_context(phb, bdf);
+	if (phb->phb_type == phb_type_npu_v2)
+		return npu2_destroy_context(phb, bdf);
+
+	if (phb->phb_type == phb_type_npu_v3)
+		return npu3_destroy_context(phb, bdf);
+
+	return OPAL_PARAMETER;
 }
 opal_call(OPAL_NPU_DESTROY_CONTEXT, opal_npu_destroy_context, 3);
 
@@ -48,10 +61,16 @@ static int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
 {
 	struct phb *phb = pci_get_phb(phb_id);
 
-	if (!phb || phb->phb_type != phb_type_npu_v2)
+	if (!phb)
 		return OPAL_PARAMETER;
 
-	return npu2_map_lpar(phb, bdf, lparid, lpcr);
+	if (phb->phb_type == phb_type_npu_v2)
+		return npu2_map_lpar(phb, bdf, lparid, lpcr);
+
+	if (phb->phb_type == phb_type_npu_v3)
+		return npu3_map_lpar(phb, bdf, lparid, lpcr);
+
+	return OPAL_PARAMETER;
 }
 opal_call(OPAL_NPU_MAP_LPAR, opal_npu_map_lpar, 4);
 
@@ -81,10 +100,13 @@ static int64_t npu_set_relaxed_order(uint32_t gcid, int pec, bool enable)
 	int64_t rc;
 
 	for_each_phb(phb) {
-		if (phb->phb_type != phb_type_npu_v2)
+		if (phb->phb_type == phb_type_npu_v2)
+			rc = npu2_set_relaxed_order(phb, gcid, pec, enable);
+		else if (phb->phb_type == phb_type_npu_v3)
+			rc = npu3_set_relaxed_order(phb, gcid, pec, enable);
+		else
 			continue;
 
-		rc = npu2_set_relaxed_order(phb, gcid, pec, enable);
 		if (rc)
 			return rc;
 	}