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hw/p8-i2c: Clean up interrupt masking
There's three interrupt registers defined for the I2C master: 1. Interrupt mask 2. Raw interrupt condition bits 3. Masked interrupt condition bits All the I2C master interrupts are LSIs so the raw condition bits will only go to zero if the interrupt condition is dealt with. As a result the latter two registers are read only. For writes their addresses are re-used as atomic OR and atomic AND update registers for the mask register. When unmasking interrupts we currently do that via the atomic OR register and mask via the atomic AND, but we use the interrupt condition register macro names. This is a bit confusing and the documentation isn't super clear about the behaviour so fix the macro names in favour of something saner. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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