psi: update registers to reflect >= P8 PHBSCR

Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
open-power · Nov 11, 2019 · ef7c7de · ef7c7de
1 parent 4055879
commit ef7c7de
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Showing 2 changed files with 5 additions and 19 deletions.
diff --git a/hw/fsp/fsp-psi.c b/hw/fsp/fsp-psi.c
@@ -8,24 +8,14 @@
 
 static void psi_tce_enable(struct psi *psi, bool enable)
 {
-	void *addr;
+	void *addr = psi->regs + PSIHB_PHBSCR;
 	u64 val;
 
-	switch (proc_gen) {
-	case proc_gen_p8:
-	case proc_gen_p9:
-		addr = psi->regs + PSIHB_PHBSCR;
-		break;
-	default:
-		prerror("%s: Unknown CPU type\n", __func__);
-		return;
-	}
-
 	val = in_be64(addr);
 	if (enable)
-		val |=  PSIHB_CR_TCE_ENABLE;
+		val |=  PSIHB_PHBSCR_TCE_ENABLE;
 	else
-		val &= ~PSIHB_CR_TCE_ENABLE;
+		val &= ~PSIHB_PHBSCR_TCE_ENABLE;
 	out_be64(addr, val);
 }
 

diff --git a/include/psi.h b/include/psi.h
@@ -32,15 +32,10 @@
 #define  PSIHB_TAR_256K_ENTRIES		2 /* P8 only */
 #define  PSIHB_TAR_512K_ENTRIES		4 /* P8 only */
 
-/* PSI Host Bridge Control Register
- *
- * note: TCE_ENABLE moved to the new PSIHB_PHBSCR on P8 but is
- * the same bit position
- */
+/* PSI Host Bridge Control Register */
 #define PSIHB_CR			0x20
 #define   PSIHB_CR_FSP_CMD_ENABLE	PPC_BIT(0)
 #define   PSIHB_CR_FSP_MMIO_ENABLE	PPC_BIT(1)
-#define   PSIHB_CR_TCE_ENABLE		PPC_BIT(2)
 #define   PSIHB_CR_FSP_IRQ_ENABLE	PPC_BIT(3)
 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE	PPC_BIT(4)
 #define   PSIHB_CR_PSI_LINK_ENABLE	PPC_BIT(5)
@@ -91,6 +86,7 @@
 
 /* Secure version of CR for P8 and P9 (TCE enable bit) */
 #define PSIHB_PHBSCR			0x90
+#define   PSIHB_PHBSCR_TCE_ENABLE	PPC_BIT(2)
 
 /* P9 registers */