Merge pull request #6 from ytakeuch/dot11zynq

fix unsigned signals to signed signals
open-sdr · Jan 28, 2023 · 19acdbe · 19acdbe
2 parents 5837538 + 7e8b444
commit 19acdbe
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/verilog/dot11.v b/verilog/dot11.v
@@ -19,12 +19,12 @@ module dot11 (
     //input [31:0] set_data,
 
     // add ports for register based inputs
-    input [10:0] power_thres,
+    input signed [10:0] power_thres,
     input [31:0] min_plateau,
     input threshold_scale,
 
     // INPUT: RSSI
-    input [10:0] rssi_half_db,
+    input signed [10:0] rssi_half_db,
     // INPUT: I/Q sample
     input [31:0] sample_in,
     input sample_in_strobe,