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coretypes.h
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coretypes.h
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/*
* CoreFreq
* Copyright (C) 2015-2022 CYRIL INGENIERIE
* Licenses: GPL2
*/
#define COREFREQ_MAJOR 1
#define COREFREQ_MINOR 92
#define COREFREQ_REV 4
#if !defined(CORE_COUNT)
#define CORE_COUNT 256
#elif !(CORE_COUNT == 64 || CORE_COUNT == 128 || CORE_COUNT == 256 \
|| CORE_COUNT == 512 || CORE_COUNT == 1024)
#error "CORE_COUNT must be 64, 128, 256, 512 or 1024"
#endif
enum CRC_MANUFACTURER
{
CRC_INTEL = 0x75a2ba39,
CRC_AMD = 0x3485bbd3,
CRC_HYGON = 0x18044630,
CRC_KVM = 0x0e8c8561,
CRC_VBOX = 0x5091f045,
CRC_KBOX = 0x02b76f04,
CRC_VMWARE = 0x2a974552,
CRC_HYPERV = 0x543a585e
};
enum { GenuineArch = 0,
AMD_Family_0Fh,
AMD_Family_10h,
AMD_Family_11h,
AMD_Family_12h,
AMD_Family_14h,
AMD_Family_15h,
AMD_Family_16h,
AMD_Family_17h,
Hygon_Family_18h,
AMD_Family_19h,
Core_Yonah,
Core_Conroe,
Core_Kentsfield,
Core_Conroe_616,
Core_Penryn,
Core_Dunnington,
Atom_Bonnell,
Atom_Silvermont,
Atom_Lincroft,
Atom_Clover_Trail,
Atom_Saltwell,
Silvermont_Bay_Trail,
Atom_Avoton,
Atom_Airmont,
Atom_Goldmont,
Atom_Sofia,
Atom_Merrifield,
Atom_Moorefield,
Nehalem_Bloomfield,
Nehalem_Lynnfield,
Nehalem_MB,
Nehalem_EX,
Westmere,
Westmere_EP,
Westmere_EX,
SandyBridge,
SandyBridge_EP,
IvyBridge,
IvyBridge_EP,
Haswell_DT,
Haswell_EP,
Haswell_ULT,
Haswell_ULX,
Broadwell,
Broadwell_D,
Broadwell_H,
Broadwell_EP,
Skylake_UY,
Skylake_S,
Skylake_X,
Xeon_Phi,
Kabylake,
Kabylake_UY,
Cannonlake_U,
Cannonlake_H,
Geminilake,
Icelake,
Icelake_UY,
Icelake_X,
Icelake_D,
Sunny_Cove,
Tigerlake,
Tigerlake_U,
Cometlake,
Cometlake_UY,
Atom_Denverton,
Tremont_Jacobsville,
Tremont_Lakefield,
Tremont_Elkhartlake,
Tremont_Jasperlake,
Sapphire_Rapids,
Rocketlake,
Rocketlake_U,
Alderlake_S,
Alderlake_H,
Alderlake_N,
Meteorlake_M,
Meteorlake_N,
Meteorlake_S,
Raptorlake,
Raptorlake_P,
Raptorlake_S,
AMD_Zen,
AMD_Zen_APU,
AMD_ZenPlus,
AMD_ZenPlus_APU,
AMD_Zen_Dali,
AMD_EPYC_Rome_CPK,
AMD_Zen2_Renoir,
AMD_Zen2_LCN,
AMD_Zen2_MTS,
AMD_Zen2_Ariel,
AMD_Zen2_Jupiter,
AMD_Zen2_MDN,
AMD_Zen3_VMR,
AMD_Zen3_CZN,
AMD_EPYC_Milan,
AMD_Zen3_Chagall,
AMD_Zen3_Badami,
AMD_Zen3Plus_RMB,
AMD_Zen4_Genoa,
AMD_Zen4_RPL,
ARCHITECTURES
};
enum HYBRID_ARCH {
Hybrid_RSVD1 = 0x10,
Hybrid_Atom = 0x20,
Hybrid_RSVD2 = 0x30,
Hybrid_Core = 0x40
};
enum HYPERVISOR {
HYPERV_NONE,
BARE_METAL,
HYPERV_XEN,
HYPERV_KVM,
HYPERV_VBOX,
HYPERV_KBOX,
HYPERV_VMWARE,
HYPERV_HYPERV
};
#define HYPERVISORS ( 1 + HYPERV_HYPERV )
enum SYS_REG {
RFLAG_TF = 8,
RFLAG_IF = 9,
RFLAG_IOPL = 12, /* [13:12] */
RFLAG_NT = 14,
RFLAG_RF = 16,
RFLAG_VM = 17,
RFLAG_AC = 18,
RFLAG_VIF = 19,
RFLAG_VIP = 20,
RFLAG_ID = 21,
CR0_PE = 0,
CR0_MP = 1,
CR0_EM = 2,
CR0_TS = 3,
CR0_ET = 4,
CR0_NE = 5,
CR0_WP = 16,
CR0_AM = 18,
CR0_NW = 29,
CR0_CD = 30,
CR0_PG = 31,
CR3_PWT = 3,
CR3_PCD = 4,
CR4_VME = 0,
CR4_PVI = 1,
CR4_TSD = 2,
CR4_DE = 3,
CR4_PSE = 4,
CR4_PAE = 5,
CR4_MCE = 6,
CR4_PGE = 7,
CR4_PCE = 8,
CR4_OSFXSR = 9,
CR4_OSXMMEXCPT = 10,
CR4_UMIP = 11,
CR4_LA57 = 12,
CR4_VMXE = 13,
CR4_SMXE = 14,
CR4_FSGSBASE = 16,
CR4_PCIDE = 17,
CR4_OSXSAVE = 18,
CR4_KL = 19,
CR4_SMEP = 20,
CR4_SMAP = 21,
CR4_PKE = 22,
CR4_CET = 23,
CR4_PKS = 24,
CR8_TPL = 0, /* [3:0] */
EXFCR_LOCK = 0,
EXFCR_VMX_IN_SMX= 1,
EXFCR_VMXOUT_SMX= 2,
EXFCR_SENTER_LEN= 8, /* [14:8] */
EXFCR_SENTER_GEN= 15,
EXFCR_SGX_LCE = 17,
EXFCR_SGX_GEN = 18,
EXFCR_LMCE = 20,
EXFER_SCE = 0,
EXFER_LME = 8,
EXFER_LMA = 10,
EXFER_NXE = 11,
EXFER_SVME = 12, /* AMD F17h */
EXFER_LMSLE = 13, /* AMD F17h */
EXFER_FFXSE = 14, /* AMD F17h */
EXFER_TCE = 15, /* AMD F17h */
EXFER_MCOMMIT = 17, /* AMD F17h */
EXFER_INT_WBINVD= 18, /* AMD F17h */
UNDEF_CR = 64
};
enum CSTATES_ENCODING {
_C0 = 0x0,
_C1 = 0x1,
_C2 = 0x2,
_C3 = 0x3,
_C4 = 0x4,
_C6 = 0x6,
_C6R = 0xb,
_C7 = 0x7,
_C7S = 0xc,
_C8 = 0x8,
_C9 = 0x9,
_C10 = 0xa,
_UNSPEC = 0xf
};
#define CSTATES_ENCODING_COUNT 12
enum THM_POINTS {
THM_THRESHOLD_1,
THM_THRESHOLD_2,
THM_TRIP_LIMIT,
THM_HTC_LIMIT,
THM_HTC_HYST,
THM_POINTS_DIM
};
typedef struct
{
Bit64 Mask, /* 1=Thermal Point is specified */
Kind, /* 0=Threshold ; 1=Limit */
State __attribute__ ((aligned (8))); /*1=Enabled*/
unsigned short Value[THM_POINTS_DIM];
} THERMAL_POINT;
enum EVENT_LOG {
/* MSR_IA32_{PACKAGE}_THERM_STATUS: x8 */
LSHIFT_THERMAL_LOG,
LSHIFT_PROCHOT_LOG,
LSHIFT_CRITIC_LOG,
LSHIFT_THOLD1_LOG,
LSHIFT_THOLD2_LOG,
LSHIFT_POWER_LIMIT,
LSHIFT_CURRENT_LIMIT,
LSHIFT_CROSS_DOMAIN,
/* MSR_SKL_CORE_PERF_LIMIT_REASONS: x11 */
LSHIFT_CORE_HOT_LOG,
LSHIFT_CORE_THM_LOG,
LSHIFT_CORE_RES_LOG,
LSHIFT_CORE_AVG_LOG,
LSHIFT_CORE_VRT_LOG,
LSHIFT_CORE_TDC_LOG,
LSHIFT_CORE_PL1_LOG,
LSHIFT_CORE_PL2_LOG,
LSHIFT_CORE_EDP_LOG,
LSHIFT_CORE_BST_LOG,
LSHIFT_CORE_ATT_LOG,
LSHIFT_CORE_TVB_LOG,
/* MSR_GRAPHICS_PERF_LIMIT_REASONS: x9 */
LSHIFT_GFX_HOT_LOG,
LSHIFT_GFX_THM_LOG,
LSHIFT_GFX_AVG_LOG,
LSHIFT_GFX_VRT_LOG,
LSHIFT_GFX_TDC_LOG,
LSHIFT_GFX_PL1_LOG,
LSHIFT_GFX_PL2_LOG,
LSHIFT_GFX_EDP_LOG,
LSHIFT_GFX_EFF_LOG,
/* MSR_RING_PERF_LIMIT_REASONS: x8 */
LSHIFT_RING_HOT_LOG,
LSHIFT_RING_THM_LOG,
LSHIFT_RING_AVG_LOG,
LSHIFT_RING_VRT_LOG,
LSHIFT_RING_TDC_LOG,
LSHIFT_RING_PL1_LOG,
LSHIFT_RING_PL2_LOG,
LSHIFT_RING_EDP_LOG
};
enum EVENT_STS {
/* MSR_IA32_{PACKAGE}_THERM_STATUS: x4 */
LSHIFT_THERMAL_STS,
LSHIFT_PROCHOT_STS,
LSHIFT_CRITIC_TMP,
LSHIFT_THOLD1_STS,
LSHIFT_THOLD2_STS,
/* MSR_SKL_CORE_PERF_LIMIT_REASONS: x11 */
LSHIFT_CORE_THM_STS,
LSHIFT_CORE_HOT_STS,
LSHIFT_CORE_RES_STS,
LSHIFT_CORE_AVG_STS,
LSHIFT_CORE_VRT_STS,
LSHIFT_CORE_TDC_STS,
LSHIFT_CORE_PL1_STS,
LSHIFT_CORE_PL2_STS,
LSHIFT_CORE_EDP_STS,
LSHIFT_CORE_BST_STS,
LSHIFT_CORE_ATT_STS,
LSHIFT_CORE_TVB_STS,
/* MSR_GRAPHICS_PERF_LIMIT_REASONS: x9 */
LSHIFT_GFX_THM_STS,
LSHIFT_GFX_HOT_STS,
LSHIFT_GFX_AVG_STS,
LSHIFT_GFX_VRT_STS,
LSHIFT_GFX_TDC_STS,
LSHIFT_GFX_PL1_STS,
LSHIFT_GFX_PL2_STS,
LSHIFT_GFX_EDP_STS,
LSHIFT_GFX_EFF_STS,
/* MSR_RING_PERF_LIMIT_REASONS: x8 */
LSHIFT_RING_THM_STS,
LSHIFT_RING_HOT_STS,
LSHIFT_RING_AVG_STS,
LSHIFT_RING_VRT_STS,
LSHIFT_RING_TDC_STS,
LSHIFT_RING_PL1_STS,
LSHIFT_RING_PL2_STS,
LSHIFT_RING_EDP_STS
};
enum {
eLOG,
eSTS,
eDIM
};
enum THERM_PWR_EVENTS {
EVENT_THERM_NONE = 0x0LLU,
/* MSR_IA32_{PACKAGE}_THERM_STATUS: */
EVENT_THERMAL_STS = 0x1LLU << LSHIFT_THERMAL_STS,
EVENT_THERMAL_LOG = 0x1LLU << LSHIFT_THERMAL_LOG,
EVENT_PROCHOT_STS = 0x1LLU << LSHIFT_PROCHOT_STS,
EVENT_PROCHOT_LOG = 0x1LLU << LSHIFT_PROCHOT_LOG,
EVENT_CRITIC_TMP = 0x1LLU << LSHIFT_CRITIC_TMP,
EVENT_CRITIC_LOG = 0x1LLU << LSHIFT_CRITIC_LOG,
EVENT_THOLD1_STS = 0x1LLU << LSHIFT_THOLD1_STS,
EVENT_THOLD2_STS = 0x1LLU << LSHIFT_THOLD2_STS,
EVENT_THOLD1_LOG = 0x1LLU << LSHIFT_THOLD1_LOG,
EVENT_THOLD2_LOG = 0x1LLU << LSHIFT_THOLD2_LOG,
EVENT_POWER_LIMIT = 0x1LLU << LSHIFT_POWER_LIMIT,
EVENT_CURRENT_LIMIT = 0x1LLU << LSHIFT_CURRENT_LIMIT,
EVENT_CROSS_DOMAIN = 0x1LLU << LSHIFT_CROSS_DOMAIN,
/* MSR_SKL_CORE_PERF_LIMIT_REASONS: */
EVENT_CORE_THM_STS = 0x1LLU << LSHIFT_CORE_THM_STS,
EVENT_CORE_HOT_STS = 0x1LLU << LSHIFT_CORE_HOT_STS,
EVENT_CORE_HOT_LOG = 0x1LLU << LSHIFT_CORE_HOT_LOG,
EVENT_CORE_THM_LOG = 0x1LLU << LSHIFT_CORE_THM_LOG,
EVENT_CORE_RES_STS = 0x1LLU << LSHIFT_CORE_RES_STS,
EVENT_CORE_RES_LOG = 0x1LLU << LSHIFT_CORE_RES_LOG,
EVENT_CORE_AVG_STS = 0x1LLU << LSHIFT_CORE_AVG_STS,
EVENT_CORE_AVG_LOG = 0x1LLU << LSHIFT_CORE_AVG_LOG,
EVENT_CORE_VRT_STS = 0x1LLU << LSHIFT_CORE_VRT_STS,
EVENT_CORE_VRT_LOG = 0x1LLU << LSHIFT_CORE_VRT_LOG,
EVENT_CORE_TDC_STS = 0x1LLU << LSHIFT_CORE_TDC_STS,
EVENT_CORE_TDC_LOG = 0x1LLU << LSHIFT_CORE_TDC_LOG,
EVENT_CORE_PL1_STS = 0x1LLU << LSHIFT_CORE_PL1_STS,
EVENT_CORE_PL1_LOG = 0x1LLU << LSHIFT_CORE_PL1_LOG,
EVENT_CORE_PL2_STS = 0x1LLU << LSHIFT_CORE_PL2_STS,
EVENT_CORE_PL2_LOG = 0x1LLU << LSHIFT_CORE_PL2_LOG,
EVENT_CORE_EDP_STS = 0x1LLU << LSHIFT_CORE_EDP_STS,
EVENT_CORE_EDP_LOG = 0x1LLU << LSHIFT_CORE_EDP_LOG,
EVENT_CORE_BST_STS = 0x1LLU << LSHIFT_CORE_BST_STS,
EVENT_CORE_BST_LOG = 0x1LLU << LSHIFT_CORE_BST_LOG,
EVENT_CORE_ATT_STS = 0x1LLU << LSHIFT_CORE_ATT_STS,
EVENT_CORE_ATT_LOG = 0x1LLU << LSHIFT_CORE_ATT_LOG,
EVENT_CORE_TVB_STS = 0x1LLU << LSHIFT_CORE_TVB_STS,
EVENT_CORE_TVB_LOG = 0x1LLU << LSHIFT_CORE_TVB_LOG,
/* MSR_GRAPHICS_PERF_LIMIT_REASONS: */
EVENT_GFX_THM_STS = 0x1LLU << LSHIFT_GFX_THM_STS,
EVENT_GFX_HOT_STS = 0x1LLU << LSHIFT_GFX_HOT_STS,
EVENT_GFX_HOT_LOG = 0x1LLU << LSHIFT_GFX_HOT_LOG,
EVENT_GFX_THM_LOG = 0x1LLU << LSHIFT_GFX_THM_LOG,
EVENT_GFX_AVG_STS = 0x1LLU << LSHIFT_GFX_AVG_STS,
EVENT_GFX_AVG_LOG = 0x1LLU << LSHIFT_GFX_AVG_LOG,
EVENT_GFX_VRT_STS = 0x1LLU << LSHIFT_GFX_VRT_STS,
EVENT_GFX_VRT_LOG = 0x1LLU << LSHIFT_GFX_VRT_LOG,
EVENT_GFX_TDC_STS = 0x1LLU << LSHIFT_GFX_TDC_STS,
EVENT_GFX_TDC_LOG = 0x1LLU << LSHIFT_GFX_TDC_LOG,
EVENT_GFX_PL1_STS = 0x1LLU << LSHIFT_GFX_PL1_STS,
EVENT_GFX_PL1_LOG = 0x1LLU << LSHIFT_GFX_PL1_LOG,
EVENT_GFX_PL2_STS = 0x1LLU << LSHIFT_GFX_PL2_STS,
EVENT_GFX_PL2_LOG = 0x1LLU << LSHIFT_GFX_PL2_LOG,
EVENT_GFX_EDP_STS = 0x1LLU << LSHIFT_GFX_EDP_STS,
EVENT_GFX_EDP_LOG = 0x1LLU << LSHIFT_GFX_EDP_LOG,
EVENT_GFX_EFF_STS = 0x1LLU << LSHIFT_GFX_EFF_STS,
EVENT_GFX_EFF_LOG = 0x1LLU << LSHIFT_GFX_EFF_LOG,
/* MSR_RING_PERF_LIMIT_REASONS: */
EVENT_RING_THM_STS = 0x1LLU << LSHIFT_RING_THM_STS,
EVENT_RING_HOT_STS = 0x1LLU << LSHIFT_RING_HOT_STS,
EVENT_RING_HOT_LOG = 0x1LLU << LSHIFT_RING_HOT_LOG,
EVENT_RING_THM_LOG = 0x1LLU << LSHIFT_RING_THM_LOG,
EVENT_RING_AVG_STS = 0x1LLU << LSHIFT_RING_AVG_STS,
EVENT_RING_AVG_LOG = 0x1LLU << LSHIFT_RING_AVG_LOG,
EVENT_RING_VRT_STS = 0x1LLU << LSHIFT_RING_VRT_STS,
EVENT_RING_VRT_LOG = 0x1LLU << LSHIFT_RING_VRT_LOG,
EVENT_RING_TDC_STS = 0x1LLU << LSHIFT_RING_TDC_STS,
EVENT_RING_TDC_LOG = 0x1LLU << LSHIFT_RING_TDC_LOG,
EVENT_RING_PL1_STS = 0x1LLU << LSHIFT_RING_PL1_STS,
EVENT_RING_PL1_LOG = 0x1LLU << LSHIFT_RING_PL1_LOG,
EVENT_RING_PL2_STS = 0x1LLU << LSHIFT_RING_PL2_STS,
EVENT_RING_PL2_LOG = 0x1LLU << LSHIFT_RING_PL2_LOG,
EVENT_RING_EDP_STS = 0x1LLU << LSHIFT_RING_EDP_STS,
EVENT_RING_EDP_LOG = 0x1LLU << LSHIFT_RING_EDP_LOG,
/* ALL EVENTS */
EVENT_ALL_OF_THEM = EVENT_RING_EDP_LOG << 1
};
enum SENSOR_LIMITS {
SENSOR_LOWEST,
SENSOR_HIGHEST,
SENSOR_LIMITS_DIM
};
typedef union
{
unsigned long Target;
unsigned short Offset[3];
} THERMAL_PARAM;
enum FORMULA_SCOPE {
FORMULA_SCOPE_NONE = 0,
FORMULA_SCOPE_SMT = 1,
FORMULA_SCOPE_CORE = 2,
FORMULA_SCOPE_PKG = 3
};
enum THERMAL_KIND {
THERMAL_KIND_NONE = 0b000000000000000000000000,
THERMAL_KIND_INTEL = 0b000000000000000000000001,
THERMAL_KIND_AMD = 0b000000000001000000000000,
THERMAL_KIND_AMD_0Fh = 0b000000000011000000000000,
THERMAL_KIND_AMD_15h = 0b000001000001000000000000,
THERMAL_KIND_AMD_17h = 0b000100000001000000000000
};
enum THERMAL_FORMULAS {
THERMAL_FORMULA_NONE = (THERMAL_KIND_NONE << 8) | FORMULA_SCOPE_NONE,
THERMAL_FORMULA_INTEL = (THERMAL_KIND_INTEL << 8) | FORMULA_SCOPE_SMT,
THERMAL_FORMULA_AMD = (THERMAL_KIND_AMD << 8) | FORMULA_SCOPE_SMT,
THERMAL_FORMULA_AMD_0Fh = (THERMAL_KIND_AMD_0Fh << 8) | FORMULA_SCOPE_SMT,
THERMAL_FORMULA_AMD_15h = (THERMAL_KIND_AMD_15h << 8) | FORMULA_SCOPE_CORE,
THERMAL_FORMULA_AMD_17h = (THERMAL_KIND_AMD_17h << 8) | FORMULA_SCOPE_PKG,
THERMAL_FORMULA_AMD_ZEN2= (THERMAL_KIND_AMD_17h << 8) | FORMULA_SCOPE_SMT
};
#define THERMAL_FORMULA_AMD_19h THERMAL_FORMULA_AMD_17h
#define THERMAL_FORMULA_AMD_ZEN3 THERMAL_FORMULA_AMD_ZEN2
enum VOLTAGE_KIND {
VOLTAGE_KIND_NONE = 0b000000000000000000000000,
VOLTAGE_KIND_INTEL = 0b000000000000000000000001,
VOLTAGE_KIND_INTEL_CORE2= 0b000000000000000000000011,
VOLTAGE_KIND_INTEL_SOC = 0b000000000000000000000111,
VOLTAGE_KIND_INTEL_SNB = 0b000000000000000010000001,
VOLTAGE_KIND_INTEL_SKL_X= 0b000000000000010000000001,
VOLTAGE_KIND_INTEL_SAV = 0b000000000000000100000001,
VOLTAGE_KIND_AMD = 0b000000000001000000000000,
VOLTAGE_KIND_AMD_0Fh = 0b000000000011000000000000,
VOLTAGE_KIND_AMD_15h = 0b000001000001000000000000,
VOLTAGE_KIND_AMD_17h = 0b000100000001000000000000,
VOLTAGE_KIND_AMD_RMB = 0b000010000001000000000000,
VOLTAGE_KIND_WINBOND_IO = 0b001000000000000000000000,
VOLTAGE_KIND_ITETECH_IO = 0b010000000000000000000000
};
enum VOLTAGE_FORMULAS {
VOLTAGE_FORMULA_NONE =(VOLTAGE_KIND_NONE << 8) | FORMULA_SCOPE_NONE,
VOLTAGE_FORMULA_INTEL =(VOLTAGE_KIND_INTEL << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_INTEL_CORE2=(VOLTAGE_KIND_INTEL_CORE2 << 8)| FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_INTEL_SOC =(VOLTAGE_KIND_INTEL_SOC << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_INTEL_SNB =(VOLTAGE_KIND_INTEL_SNB << 8) | FORMULA_SCOPE_PKG,
VOLTAGE_FORMULA_INTEL_SNB_E=(VOLTAGE_KIND_INTEL_SNB << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_INTEL_SKL_X=(VOLTAGE_KIND_INTEL_SKL_X << 8)| FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_INTEL_SAV =(VOLTAGE_KIND_INTEL_SAV << 8) | FORMULA_SCOPE_CORE,
VOLTAGE_FORMULA_AMD =(VOLTAGE_KIND_AMD << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_AMD_0Fh =(VOLTAGE_KIND_AMD_0Fh << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_AMD_15h =(VOLTAGE_KIND_AMD_15h << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_AMD_17h =(VOLTAGE_KIND_AMD_17h << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_AMD_RMB =(VOLTAGE_KIND_AMD_RMB << 8) | FORMULA_SCOPE_PKG,
VOLTAGE_FORMULA_WINBOND_IO =(VOLTAGE_KIND_WINBOND_IO << 8) | FORMULA_SCOPE_PKG,
VOLTAGE_FORMULA_ITETECH_IO =(VOLTAGE_KIND_ITETECH_IO << 8) | FORMULA_SCOPE_PKG
};
#define VOLTAGE_FORMULA_AMD_19h VOLTAGE_FORMULA_AMD_17h
enum POWER_KIND {
POWER_KIND_NONE = 0b000000000000000000000000,
POWER_KIND_INTEL = 0b000000000000000000000001,
POWER_KIND_INTEL_ATOM = 0b000000000000000000000011,
POWER_KIND_AMD = 0b000000000001000000000000,
POWER_KIND_AMD_17h = 0b000100000001000000000000
};
enum POWER_FORMULAS {
POWER_FORMULA_NONE =(POWER_KIND_NONE << 8) | FORMULA_SCOPE_NONE,
POWER_FORMULA_INTEL =(POWER_KIND_INTEL << 8) | FORMULA_SCOPE_NONE,
POWER_FORMULA_INTEL_ATOM=(POWER_KIND_INTEL_ATOM << 8) | FORMULA_SCOPE_NONE,
POWER_FORMULA_AMD =(POWER_KIND_AMD << 8) | FORMULA_SCOPE_CORE,
POWER_FORMULA_AMD_17h =(POWER_KIND_AMD_17h << 8) | FORMULA_SCOPE_CORE
};
#define POWER_FORMULA_AMD_19h POWER_FORMULA_AMD_17h
#define SCOPE_OF_FORMULA(formula) (formula & 0b0011)
#define KIND_OF_FORMULA(formula) ((formula >> 8) & 0b111111111111111111111111)
/* Sensors formulas and definitions.
MIN = [SENSOR] > [TRIGGER] AND ([SENSOR] < [LOWEST] OR [LOWEST] <= [CAPPED])
MAX = [SENSOR] > [HIGHEST]
*/
#define THRESHOLD_LOWEST_CAPPED_THERMAL 1
#define THRESHOLD_LOWEST_CAPPED_VOLTAGE 0.15
#define THRESHOLD_LOWEST_CAPPED_ENERGY 0.000001
#define THRESHOLD_LOWEST_CAPPED_POWER 0.000001
#define THRESHOLD_LOWEST_CAPPED_REL_FREQ 0.0
#define THRESHOLD_LOWEST_CAPPED_ABS_FREQ 0.0
#define THRESHOLD_LOWEST_TRIGGER_THERMAL 0
#define THRESHOLD_LOWEST_TRIGGER_VOLTAGE 0.0
#define THRESHOLD_LOWEST_TRIGGER_ENERGY 0.0
#define THRESHOLD_LOWEST_TRIGGER_POWER 0.0
#define THRESHOLD_LOWEST_TRIGGER_REL_FREQ 0.0
#define THRESHOLD_LOWEST_TRIGGER_ABS_FREQ 0.0
#define _RESET_SENSOR_LIMIT(THRESHOLD, Limit) \
({ \
Limit = THRESHOLD; \
})
#define RESET_SENSOR_LOWEST(CLASS, Limit) \
_RESET_SENSOR_LIMIT(THRESHOLD_LOWEST_CAPPED_##CLASS, \
Limit[SENSOR_LOWEST])
#define RESET_SENSOR_HIGHEST(CLASS, Limit) \
_RESET_SENSOR_LIMIT(THRESHOLD_LOWEST_TRIGGER_##CLASS, \
Limit[SENSOR_HIGHEST])
#define RESET_SENSOR_LIMIT(CLASS, STAT, Limit) \
RESET_SENSOR_##STAT(CLASS, Limit)
#define TEST_SENSOR_LOWEST(CLASS, TRIGGER, CAPPED, Sensor, Limit) \
(Sensor > TRIGGER##CLASS) \
&& ((Sensor < Limit) || (Limit <= CAPPED##CLASS))
#define TEST_SENSOR_HIGHEST(CLASS, TRIGGER, CAPPED, Sensor, Limit) \
(Sensor > Limit)
#define _TEST_SENSOR(CLASS, STAT, THRESHOLD, TRIGGER, CAPPED, Sensor, Limit) \
TEST_SENSOR_##STAT(CLASS, THRESHOLD##TRIGGER, THRESHOLD##CAPPED, \
Sensor, Limit)
#define TEST_SENSOR(CLASS, STAT, Sensor, Limit) \
_TEST_SENSOR(CLASS, STAT, THRESHOLD_##STAT, _TRIGGER_, _CAPPED_, \
Sensor, Limit[SENSOR_##STAT])
#define TEST_AND_SET_SENSOR(CLASS, STAT, Sensor, Limit) \
({ \
if (TEST_SENSOR(CLASS, STAT, Sensor, Limit)) \
{ \
Limit[SENSOR_##STAT] = Sensor; \
} \
})
#define COMPUTE_THERMAL_INVERSE_INTEL(Sensor, Param, Temp) \
(Sensor = Param.Offset[0] - Param.Offset[1] - Temp)
#define COMPUTE_THERMAL_INTEL(Temp, Param, Sensor) \
(Temp = Param.Offset[0] - Param.Offset[1] - Sensor)
#define COMPUTE_THERMAL_AMD(Temp, Param, Sensor) \
UNUSED(Param); \
UNUSED(Sensor); \
/*( TODO )*/
#define COMPUTE_THERMAL_AMD_0Fh(Temp, Param, Sensor) \
(Temp = Sensor - (Param.Target * 2) - 49)
#define COMPUTE_THERMAL_AMD_15h(Temp, Param, Sensor) \
UNUSED(Param); \
(Temp = Sensor * 5 / 40)
#define COMPUTE_THERMAL_AMD_17h(Temp, Param, Sensor) \
(Temp = ((Sensor * 5 / 40) - Param.Offset[1]) - Param.Offset[2])
#define COMPUTE_THERMAL(_ARCH_, Temp, Param, Sensor) \
COMPUTE_THERMAL_##_ARCH_(Temp, Param, Sensor)
#define COMPUTE_VOLTAGE_INTEL_CORE2(Vcore, VID) \
(Vcore = 0.8875 + (double) (VID) * 0.0125)
#define COMPUTE_VOLTAGE_INTEL_SOC(Vcore, VID) \
({ \
switch (VID) { \
case 0x00: \
Vcore = 0.0f; \
break; \
case 0xfc: \
case 0xfe: \
Vcore = 1.495f; \
break; \
case 0xfd: \
case 0xff: \
Vcore = 1.5f; \
break; \
default: \
Vcore = 0.245 + (double) (VID) * 0.005; \
break; \
} \
})
#define COMPUTE_VOLTAGE_INTEL_SNB(Vcore, VID) \
(Vcore = (double) (VID) / 8192.0)
#define COMPUTE_VOLTAGE_INTEL_SKL_X(Vcore, VID) \
(Vcore = (double) (VID) / 8192.0)
#define COMPUTE_VOLTAGE_INTEL_SAV COMPUTE_VOLTAGE_INTEL_SNB
#define COMPUTE_VOLTAGE_AMD(Vcore, VID) \
/*( TODO )*/
#define COMPUTE_VOLTAGE_AMD_0Fh(Vcore, VID) \
({ \
short Vselect =(VID & 0b110000) >> 4, Vnibble = VID & 0b1111; \
\
switch (Vselect) { \
case 0b00: \
Vcore = 1.550 - (double) (Vnibble) * 0.025; \
break; \
case 0b01: \
Vcore = 1.150 - (double) (Vnibble) * 0.025; \
break; \
case 0b10: \
Vcore = 0.7625 - (double) (Vnibble) * 0.0125; \
break; \
case 0b11: \
Vcore = 0.5625 - (double) (Vnibble) * 0.0125; \
break; \
} \
})
#define COMPUTE_VOLTAGE_AMD_15h(Vcore, VID) \
(Vcore = 1.550 - (0.00625 * (double) (VID)))
#define COMPUTE_VOLTAGE_AMD_17h(Vcore, VID) \
(Vcore = 1.550 - (0.00625 * (double) (VID)))
#define COMPUTE_VOLTAGE_AMD_RMB(Vcore, VID) \
(Vcore = 0.00625 * (double) (VID))
#define COMPUTE_VOLTAGE_WINBOND_IO(Vcore, VID) \
(Vcore = (double) (VID) * 0.008)
#define COMPUTE_VOLTAGE_ITETECH_IO(Vcore, VID) \
(Vcore = (double) (VID) * 0.016)
#define COMPUTE_VOLTAGE(_ARCH_, Vcore, VID) \
COMPUTE_VOLTAGE_##_ARCH_(Vcore, VID)
#define COMPUTE_TAU(Y, Z, TU) ( \
(1LLU << Y) * (1.0 + Z / 4.0) * TU \
)
#define COMPUTE_TW(Y, Z) ( \
((unsigned char) Z << 5) | (unsigned char) Y \
)
enum PWR_LIMIT {
PL1 = 0,
PL2 = 1,
PWR_LIMIT_SIZE
};
enum PWR_DOMAIN {
DOMAIN_PKG = 0,
DOMAIN_CORES = 1,
DOMAIN_UNCORE = 2,
DOMAIN_RAM = 3,
DOMAIN_PLATFORM = 4,
DOMAIN_SIZE
};
#define PWR_DOMAIN(NC) DOMAIN_##NC
enum RATIO_BOOST {
RATIO_MIN,
RATIO_MAX,
RATIO_TGT,
RATIO_ACT,
RATIO_TDP,
RATIO_TDP1,
RATIO_TDP2,
RATIO_CPB = RATIO_TDP1,
RATIO_XFR = RATIO_TDP2,
RATIO_HWP_MIN,
RATIO_HWP_MAX,
RATIO_HWP_TGT,
RATIO_18C,
RATIO_17C,
RATIO_16C,
RATIO_15C,
RATIO_14C,
RATIO_13C,
RATIO_12C,
RATIO_11C,
RATIO_10C,
RATIO_9C,
RATIO_8C,
RATIO_7C,
RATIO_6C,
RATIO_5C,
RATIO_4C,
RATIO_3C,
RATIO_2C,
RATIO_1C,
RATIO_SIZE
};
#define BOOST(NC) RATIO_##NC
enum UNCORE_BOOST {
UNCORE_RATIO_MIN,
UNCORE_RATIO_MAX,
UNCORE_RATIO_SIZE
};
#define UNCORE_BOOST(NC) UNCORE_RATIO_##NC
#define CACHE_MAX_LEVEL (3 + 1)
#define PRECISION 100
#define UNIT_KHz(_f) (_f * 10 * PRECISION)
#define UNIT_MHz(_f) (_f * UNIT_KHz(1000))
#define UNIT_GHz(_f) (_f * UNIT_MHz(1000))
#define CLOCK_KHz(_t, _f) ((_t)(_f) / (_t)UNIT_KHz(1))
#define CLOCK_MHz(_t, _f) ((_t)(_f) / (_t)UNIT_MHz(1))
#define CLOCK_GHz(_t, _f) ((_t)(_f) / (_t)UNIT_GHz(1))
#if !defined(MAX_FREQ_HZ)
#define MAX_FREQ_HZ 6575000000
#elif (MAX_FREQ_HZ < 4850000000)
#error "MAX_FREQ_HZ must be at least 4850000000 Hz"
#endif
#define MAXCLOCK_TO_RATIO(_typeout, BaseClock) \
( (_typeout) (MAX_FREQ_HZ / BaseClock) )
enum OFFLINE
{
HW,
OS
};
typedef struct
{
unsigned short Q,
R;
} COF_ST;
typedef union {
unsigned int Perf; /* STATUS or BOOST P-State */
COF_ST COF;
} COF_UNION;
typedef struct
{
unsigned long long Q,
R,
Hz;
} CLOCK;
#define REL_BCLK(clock, ratio, delta_tsc, interval) \
({ /* Compute Clock (Hertz) */ \
clock.Hz = (1000LLU * delta_tsc) / (interval * ratio); \
/* Compute Quotient (MHz) */ \
clock.Q = clock.Hz / (1000LLU * 1000LLU); \
/* Compute Remainder (MHz) */ \
clock.R = clock.Hz % (1000LLU * 1000LLU); \
})
#define REL_FREQ_MHz(this_type, this_ratio, clock, interval) \
( (this_type)(clock.Hz) \
* (this_type)(this_ratio) \
* (this_type)(interval)) \
/ (this_type)UNIT_MHz(interval)
#define ABS_FREQ_MHz(this_type, this_ratio, this_clock) \
( \
CLOCK_MHz(this_type, this_ratio * this_clock.Hz) \
)
typedef union {
signed long long sllong;
unsigned long long ullong;
struct {
struct {
union {
signed short Offset;
signed short Ratio;
};
signed short cpu;
};
unsigned int NC;
};
} CLOCK_ARG;
enum CLOCK_MOD_INDEX {
CLOCK_MOD_ACT = 7,
CLOCK_MOD_HWP_MIN = 6,
CLOCK_MOD_HWP_MAX = 5,
CLOCK_MOD_HWP_TGT = 4,
CLOCK_MOD_MIN = 3,
CLOCK_MOD_MAX = 2,
CLOCK_MOD_TGT = 1
};
enum { /* Stick to the Kernel enumeration in include/asm/nmi.h */
BIT_NMI_LOCAL = 0,
BIT_NMI_UNKNOWN,
BIT_NMI_SERR,
BIT_NMI_IO_CHECK
};
#define BIT_NMI_MASK 0x0fLLU
typedef union
{
signed long long Proc;
struct {
unsigned int Core;
struct {
signed short Hybrid,
Thread;
};
};
} SERVICE_PROC;
#define RESET_SERVICE {.Core = -1U, .Thread = -1, .Hybrid = -1}
enum CPUID_ENUM {
CPUID_00000001_00000000_INSTRUCTION_SET,
/* Intel */
CPUID_00000002_00000000_CACHE_AND_TLB,
CPUID_00000003_00000000_PROC_SERIAL_NUMBER,
CPUID_00000004_00000000_CACHE_L1I,
CPUID_00000004_00000001_CACHE_L1D,
CPUID_00000004_00000002_CACHE_L2,
CPUID_00000004_00000003_CACHE_L3,
/* x86 */
CPUID_00000005_00000000_MONITOR_MWAIT,
CPUID_00000006_00000000_POWER_AND_THERMAL_MGMT,
CPUID_00000007_00000000_EXTENDED_FEATURES,
CPUID_00000007_00000001_EXT_FEAT_SUB_LEAF_1,
CPUID_00000007_00000001_EXT_FEAT_SUB_LEAF_2,
/* Intel */
CPUID_00000009_00000000_DIRECT_CACHE_ACCESS,
CPUID_0000000A_00000000_PERF_MONITORING,
/* x86 */
CPUID_0000000B_00000000_EXT_TOPOLOGY,
CPUID_0000000D_00000000_EXT_STATE_MAIN_LEAF,
CPUID_0000000D_00000001_EXT_STATE_SUB_LEAF,
/* AMD */
CPUID_0000000D_00000002_EXT_STATE_SUB_LEAF,
CPUID_0000000D_00000003_BNDREGS_STATE,
CPUID_0000000D_00000004_BNDCSR_STATE,
/* AMD Family 19h */
CPUID_0000000D_00000009_MPK_STATE_SUB_LEAF,
CPUID_0000000D_00000009_CET_U_SUB_LEAF,
CPUID_0000000D_00000009_CET_S_SUB_LEAF,
/* AMD Family 15h */
CPUID_0000000D_0000003E_EXT_STATE_SUB_LEAF,
/* Intel */
CPUID_0000000F_00000000_QOS_MONITORING_CAP,
CPUID_0000000F_00000001_L3_QOS_MONITORING,
CPUID_00000010_00000000_QOS_ENFORCEMENT_CAP,
CPUID_00000010_00000001_L3_ALLOC_ENUMERATION,
CPUID_00000010_00000002_L2_ALLOC_ENUMERATION,
CPUID_00000010_00000003_RAM_BANDWIDTH_ENUM,
CPUID_00000012_00000000_SGX_CAPABILITY,
CPUID_00000012_00000001_SGX_ATTRIBUTES,
CPUID_00000012_00000002_SGX_ENCLAVE_PAGE_CACHE,
CPUID_00000014_00000000_PROCESSOR_TRACE,
CPUID_00000014_00000001_PROC_TRACE_SUB_LEAF,
CPUID_00000015_00000000_TIME_STAMP_COUNTER,
CPUID_00000016_00000000_PROCESSOR_FREQUENCY,
CPUID_00000017_00000000_SYSTEM_ON_CHIP,
CPUID_00000017_00000001_SOC_ATTRIB_SUB_LEAF_1,
CPUID_00000017_00000002_SOC_ATTRIB_SUB_LEAF_2,
CPUID_00000017_00000003_SOC_ATTRIB_SUB_LEAF_3,
/* Intel */
CPUID_00000018_00000000_ADDRESS_TRANSLATION,
CPUID_00000018_00000001_DAT_SUB_LEAF_1,
CPUID_00000019_00000000_KEY_LOCKER,
CPUID_0000001A_00000000_HYBRID_INFORMATION,
CPUID_0000001B_00000000_PCONFIG_INFORMATION,
CPUID_0000001F_00000000_EXT_TOPOLOGY_V2,
/* x86 */
CPUID_80000001_00000000_EXTENDED_FEATURES,
CPUID_80000002_00000000_PROCESSOR_NAME_ID,
CPUID_80000003_00000000_PROCESSOR_NAME_ID,
CPUID_80000004_00000000_PROCESSOR_NAME_ID,
/* AMD */
CPUID_80000005_00000000_CACHES_L1D_L1I_TLB,
/* x86 */
CPUID_80000006_00000000_CACHE_L2_SIZE_WAY,
CPUID_80000007_00000000_ADVANCED_POWER_MGMT,
CPUID_80000008_00000000_LM_ADDRESS_SIZE,
/* AMD */
CPUID_8000000A_00000000_SVM_REVISION,
CPUID_80000019_00000000_CACHES_AND_TLB_1G,
CPUID_8000001A_00000000_PERF_OPTIMIZATION,
CPUID_8000001B_00000000_INST_BASED_SAMPLING,
CPUID_8000001C_00000000_LIGHTWEIGHT_PROFILING,
CPUID_8000001D_00000000_CACHE_L1D_PROPERTIES,
CPUID_8000001D_00000001_CACHE_L1I_PROPERTIES,
CPUID_8000001D_00000002_CACHE_L2_PROPERTIES,
CPUID_8000001D_00000003_CACHE_PROPERTIES_END,
CPUID_8000001D_00000004_CACHE_PROPERTIES_DONE,
CPUID_8000001E_00000000_EXTENDED_IDENTIFIERS,
/* AMD Family 17h */
CPUID_8000001F_00000000_SECURE_ENCRYPTION,
CPUID_80000020_00000000_MBE_SUB_LEAF,
CPUID_80000020_00000001_MBE_SUB_LEAF,
/* AMD Family 19h */
CPUID_80000021_00000000_EXTENDED_FEATURE_2,
CPUID_80000022_00000000_EXT_PERF_MON_DEBUG,
/* AMD64 Architecture Programmer’s Manual rev 4.05 */
CPUID_80000023_00000000_MULTIKEY_ENCRYPTED_MEM,
CPUID_80000026_00000000_EXTENDED_CPU_TOPOLOGY,
/* x86 */
CPUID_40000000_00000000_HYPERVISOR_VENDOR,
CPUID_40000001_00000000_HYPERVISOR_INTERFACE,
CPUID_40000002_00000000_HYPERVISOR_VERSION,
CPUID_40000003_00000000_HYPERVISOR_FEATURES,
CPUID_40000004_00000000_HYPERV_REQUIREMENTS,
CPUID_40000005_00000000_HYPERVISOR_LIMITS,
CPUID_40000006_00000000_HYPERVISOR_EXPLOITS,
CPUID_MAX_FUNC
};
typedef struct
{
unsigned int func,
sub,
reg[4];
} CPUID_STRUCT;
#define BRAND_PART 12
#define BRAND_LENGTH (4 * BRAND_PART)
#define BRAND_SIZE (BRAND_LENGTH + 4)
typedef struct
{ /* Common x86 */
unsigned int LargestStdFunc, /* Largest Standard CPUID */
LargestExtFunc, /* Largest Extended CPUID */
LargestHypFunc; /* Largest Hypervisor CPUID */
struct {
enum CRC_MANUFACTURER CRC;
char ID[12 + 4];
} Vendor, Hypervisor;
char Brand[BRAND_SIZE];
} CPUID_FUNCTION;