Litex build not reproducible

[nmk456]

Can you add the script/command used to generate the litex builds? I can't my own builds to work with the toolchain.

[hansfbaier]

Which ones in particular?

[nmk456]

I'm specifically interested in litex-ddr-stlv7325 but all of them would be nice.

[hansfbaier]

I just committed this.
I used almost the original litex target file, I only reduced the DDR3 pads to use only the first two modules,
and I had to run the build with 80MHz sys-clk.
Since that runs vivado, I copy the .v and the .init files from the build directory (.xdc only first time and then commenting out the parts that nextpnr-xilinx does not understand).

https://github.com/openXC7/demo-projects/blob/main/litex-ddr-stlv7325/sitlinv_stlv7325.py

[hansfbaier]

Very similar procedure with the other boards.

[hansfbaier]

Eventually we are going to add the toolchain to LiteX, but the toolchain packaging is not final yet, so I am hesitating with that at the moment.

[tommythorn]

Slightly off topic, but on the same design - I can build it and get the LED chasers, but is there supposed to be a serial console somewhere? The USB-C (between the SFP and RJ ports) claims to be a serial adapter (auto recognized by both macOS and Linux) but I'm not seeing anything there.

[hansfbaier]

Maybe the port changed in the new board revision, can you check if the pins in the xdc rile still match the schematic or board doc?

…

On Tue, May 2, 2023, 05:37 Tommy Thorn ***@***.***> wrote: Slightly off topic, but on the same design - I can build get and get the LED chasers, but is there supposed to be a serial console somewhere? The USB-C (between the SFP and RJ ports) claims to be a serial adapter (auto recognized by both macOS and Linux) but I'm not seeing anything there. — Reply to this email directly, view it on GitHub <#3 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AABEI74UILLZ5UHP7KXMBDLXEA3J5ANCNFSM6AAAAAAWYSWO24> . You are receiving this because you commented.Message ID: ***@***.***>

[tommythorn]

(Updated to be more readable)

Ok, I finally got a schematic and a lot has changed, to the point where stlv7325, which refers to the blue version 1.0 which isn't sold anymore, is really a different board than the current red, version 2.0. I see LiteX calls the latter "stlv7325_v2" which is clear. However the demos here will not probably not work with the v2 board. The seller shared a relevant link: litex-hub/litex-boards#498 which also has the schematic in the first comment.

FWIW, I succeed in getting a serial loopback design working using PIN L23 as FPGA TX/PC RX and K21 as PC TX/FPGA RX.

[hansemro]

Had to make the following litex-board changes for KC705 (similar for other boards as well):

1. Drop _T_DCI (for digitally controlled impedance with tristate support; referred to as 3-state DCI in UG471) from IOStandard constraints under litex_boards/platforms/<board>.py
   • Example: SSTL15_T_DCI -> SSTL15
   • For kc705, change needed here: https://github.com/litex-hub/litex-boards/blob/96175a9986432c1bddb3f0c265e9584a987673de/litex_boards/platforms/xilinx_kc705.py#L102
   • For stlv7325_v2, change needed here: https://github.com/litex-hub/litex-boards/blob/96175a9986432c1bddb3f0c265e9584a987673de/litex_boards/platforms/sitlinv_stlv7325_v2.py#L89-L93
2. Replace S7MMCM with S7PLL under litex_boards/targets/<board>.py
   • For kc705, change needed here: https://github.com/litex-hub/litex-boards/blob/96175a9986432c1bddb3f0c265e9584a987673de/litex_boards/targets/xilinx_kc705.py#L43

After updating litex-boards package, I can generate the necessary litex files with:

python3 -m litex_boards.targets.<board> --build --no-compile-gateware [OPTION]...

--no-compile-gateware avoids running vivado, but still generates everything needed for open source flow (gateware + bios).

Relevant fork: https://github.com/hansemro/litex-boards/commits/kc705_nextpnr

EDIT: added correction for T_DCI meaning

[hansfbaier]

Great, can you put this in a README of your contribution?

[hansemro]

Sure, I will get to it when I can.