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riscv_id_stage.sv
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riscv_id_stage.sv
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
////////////////////////////////////////////////////////////////////////////////
// Engineer: Renzo Andri - andrire@student.ethz.ch //
// //
// Additional contributions by: //
// Igor Loi - igor.loi@unibo.it //
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// Michael Gautschi - gautschi@iis.ee.ethz.ch //
// Davide Schiavone - pschiavo@iis.ee.ethz.ch //
// //
// Design Name: Instruction Decode Stage //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //
// Description: Decode stage of the core. It decodes the instructions //
// and hosts the register file. //
// //
////////////////////////////////////////////////////////////////////////////////
import riscv_defines::*;
import apu_core_package::*;
// Source/Destination register instruction index
`define REG_S1 19:15
`define REG_S2 24:20
`define REG_S4 31:27
`define REG_D 11:07
module riscv_id_stage
#(
parameter N_HWLP = 2,
parameter N_HWLP_BITS = $clog2(N_HWLP),
parameter PULP_SECURE = 0,
parameter FPU = 0,
parameter APU = 0,
parameter SHARED_FP = 0,
parameter SHARED_DSP_MULT = 0,
parameter SHARED_INT_DIV = 0,
parameter SHARED_FP_DIVSQRT = 0,
parameter WAPUTYPE = 0
)
(
input logic clk,
input logic rst_n,
input logic test_en_i,
input logic fregfile_disable_i,
input logic fetch_enable_i,
output logic ctrl_busy_o,
output logic core_ctrl_firstfetch_o,
output logic is_decoding_o,
// Interface to IF stage
input logic [N_HWLP-1:0] hwlp_dec_cnt_i,
input logic is_hwlp_i,
input logic instr_valid_i,
input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage
output logic instr_req_o,
// Jumps and branches
output logic branch_in_ex_o,
input logic branch_decision_i,
output logic [31:0] jump_target_o,
// IF and ID stage signals
output logic clear_instr_valid_o,
output logic pc_set_o,
output logic [2:0] pc_mux_o,
output logic [1:0] exc_pc_mux_o,
output logic trap_addr_mux_o,
input logic illegal_c_insn_i,
input logic is_compressed_i,
input logic [31:0] pc_if_i,
input logic [31:0] pc_id_i,
// Stalls
output logic halt_if_o, // controller requests a halt of the IF stage
output logic id_ready_o, // ID stage is ready for the next instruction
input logic ex_ready_i, // EX stage is ready for the next instruction
input logic wb_ready_i, // WB stage is ready for the next instruction
output logic id_valid_o, // ID stage is done
input logic ex_valid_i, // EX stage is done
// Pipeline ID/EX
output logic [31:0] pc_ex_o,
output logic [31:0] alu_operand_a_ex_o,
output logic [31:0] alu_operand_b_ex_o,
output logic [31:0] alu_operand_c_ex_o,
output logic [ 4:0] bmask_a_ex_o,
output logic [ 4:0] bmask_b_ex_o,
output logic [ 1:0] imm_vec_ext_ex_o,
output logic [ 1:0] alu_vec_mode_ex_o,
output logic [5:0] regfile_waddr_ex_o,
output logic regfile_we_ex_o,
output logic [5:0] regfile_alu_waddr_ex_o,
output logic regfile_alu_we_ex_o,
// ALU
output logic alu_en_ex_o,
output logic [ALU_OP_WIDTH-1:0] alu_operator_ex_o,
// MUL
output logic [ 2:0] mult_operator_ex_o,
output logic [31:0] mult_operand_a_ex_o,
output logic [31:0] mult_operand_b_ex_o,
output logic [31:0] mult_operand_c_ex_o,
output logic mult_en_ex_o,
output logic mult_sel_subword_ex_o,
output logic [ 1:0] mult_signed_mode_ex_o,
output logic [ 4:0] mult_imm_ex_o,
output logic [31:0] mult_dot_op_a_ex_o,
output logic [31:0] mult_dot_op_b_ex_o,
output logic [31:0] mult_dot_op_c_ex_o,
output logic [ 1:0] mult_dot_signed_ex_o,
// FPU
output logic [C_CMD-1:0] fpu_op_ex_o,
// APU
output logic apu_en_ex_o,
output logic [WAPUTYPE-1:0] apu_type_ex_o,
output logic [WOP_CPU-1:0] apu_op_ex_o,
output logic [1:0] apu_lat_ex_o,
output logic [31:0] apu_operands_ex_o [NARGS_CPU-1:0],
output logic [NDSFLAGS_CPU-1:0] apu_flags_ex_o,
output logic [5:0] apu_waddr_ex_o,
output logic [2:0][5:0] apu_read_regs_o,
output logic [2:0] apu_read_regs_valid_o,
input logic apu_read_dep_i,
output logic [1:0][5:0] apu_write_regs_o,
output logic [1:0] apu_write_regs_valid_o,
input logic apu_write_dep_i,
output logic apu_perf_dep_o,
input logic apu_busy_i,
input logic [C_RM-1:0] frm_i,
// CSR ID/EX
output logic csr_access_ex_o,
output logic [1:0] csr_op_ex_o,
input PrivLvl_t current_priv_lvl_i,
output logic csr_irq_sec_o,
output logic [5:0] csr_cause_o,
output logic csr_save_if_o,
output logic csr_save_id_o,
output logic csr_restore_mret_id_o,
output logic csr_restore_uret_id_o,
output logic csr_save_cause_o,
// hwloop signals
output logic [N_HWLP-1:0] [31:0] hwlp_start_o,
output logic [N_HWLP-1:0] [31:0] hwlp_end_o,
output logic [N_HWLP-1:0] [31:0] hwlp_cnt_o,
// hwloop signals from CS register
input logic [N_HWLP_BITS-1:0] csr_hwlp_regid_i,
input logic [2:0] csr_hwlp_we_i,
input logic [31:0] csr_hwlp_data_i,
// Interface to load store unit
output logic data_req_ex_o,
output logic data_we_ex_o,
output logic [1:0] data_type_ex_o,
output logic data_sign_ext_ex_o,
output logic [1:0] data_reg_offset_ex_o,
output logic data_load_event_ex_o,
output logic data_misaligned_ex_o,
output logic prepost_useincr_ex_o,
input logic data_misaligned_i,
// Interrupt signals
input logic irq_i,
input logic irq_sec_i,
input logic [4:0] irq_id_i,
input logic m_irq_enable_i,
input logic u_irq_enable_i,
output logic irq_ack_o,
output logic [4:0] irq_id_o,
output logic [5:0] exc_cause_o,
input logic lsu_load_err_i,
input logic lsu_store_err_i,
// Debug Unit Signals
input logic [DBG_SETS_W-1:0] dbg_settings_i,
input logic dbg_req_i,
output logic dbg_ack_o,
input logic dbg_stall_i,
output logic dbg_trap_o,
input logic dbg_reg_rreq_i,
input logic [ 5:0] dbg_reg_raddr_i,
output logic [31:0] dbg_reg_rdata_o,
input logic dbg_reg_wreq_i,
input logic [ 5:0] dbg_reg_waddr_i,
input logic [31:0] dbg_reg_wdata_i,
input logic dbg_jump_req_i,
// Forward Signals
input logic [5:0] regfile_waddr_wb_i,
input logic regfile_we_wb_i,
input logic [31:0] regfile_wdata_wb_i, // From wb_stage: selects data from data memory, ex_stage result and sp rdata
input logic [5:0] regfile_alu_waddr_fw_i,
input logic regfile_alu_we_fw_i,
input logic [31:0] regfile_alu_wdata_fw_i,
// from ALU
input logic mult_multicycle_i, // when we need multiple cycles in the multiplier and use op c as storage
// Performance Counters
output logic perf_jump_o, // we are executing a jump instruction
output logic perf_jr_stall_o, // jump-register-hazard
output logic perf_ld_stall_o // load-use-hazard
);
logic [31:0] instr;
// Decoder/Controller ID stage internal signals
logic deassert_we;
logic illegal_insn_dec;
logic ebrk_insn;
logic mret_insn_dec;
logic uret_insn_dec;
logic ecall_insn_dec;
logic pipe_flush_dec;
logic rega_used_dec;
logic regb_used_dec;
logic regc_used_dec;
logic branch_taken_ex;
logic [1:0] jump_in_id;
logic [1:0] jump_in_dec;
logic misaligned_stall;
logic jr_stall;
logic load_stall;
logic csr_apu_stall;
logic halt_id;
// Immediate decoding and sign extension
logic [31:0] imm_i_type;
logic [31:0] imm_iz_type;
logic [31:0] imm_s_type;
logic [31:0] imm_sb_type;
logic [31:0] imm_u_type;
logic [31:0] imm_uj_type;
logic [31:0] imm_z_type;
logic [31:0] imm_s2_type;
logic [31:0] imm_bi_type;
logic [31:0] imm_s3_type;
logic [31:0] imm_vs_type;
logic [31:0] imm_vu_type;
logic [31:0] imm_shuffleb_type;
logic [31:0] imm_shuffleh_type;
logic [31:0] imm_shuffle_type;
logic [31:0] imm_clip_type;
logic [31:0] imm_a; // contains the immediate for operand b
logic [31:0] imm_b; // contains the immediate for operand b
logic [31:0] jump_target; // calculated jump target (-> EX -> IF)
// Signals running between controller and exception controller
logic irq_req_ctrl, irq_sec_ctrl;
logic [4:0] irq_id_ctrl;
logic exc_ack, exc_kill;// handshake
// Register file interface
logic [5:0] regfile_addr_ra_id;
logic [5:0] regfile_addr_rb_id;
logic [5:0] regfile_addr_rc_id;
logic regfile_fp_a;
logic regfile_fp_b;
logic regfile_fp_c;
logic regfile_fp_d;
logic [5:0] regfile_waddr_id;
logic [5:0] regfile_alu_waddr_id;
logic regfile_alu_we_id;
logic [31:0] regfile_data_ra_id;
logic [31:0] regfile_data_rb_id;
logic [31:0] regfile_data_rc_id;
// ALU Control
logic alu_en;
logic [ALU_OP_WIDTH-1:0] alu_operator;
logic [2:0] alu_op_a_mux_sel;
logic [2:0] alu_op_b_mux_sel;
logic [1:0] alu_op_c_mux_sel;
logic [1:0] regc_mux;
logic [0:0] imm_a_mux_sel;
logic [3:0] imm_b_mux_sel;
logic [1:0] jump_target_mux_sel;
// Multiplier Control
logic [2:0] mult_operator; // multiplication operation selection
logic mult_en; // multiplication is used instead of ALU
logic mult_int_en; // use integer multiplier
logic mult_sel_subword; // Select a subword when doing multiplications
logic [1:0] mult_signed_mode; // Signed mode multiplication at the output of the controller, and before the pipe registers
logic mult_dot_en; // use dot product
logic [1:0] mult_dot_signed; // Signed mode dot products (can be mixed types)
// FPU signals
logic [C_CMD-1:0] fpu_op;
// APU signals
logic apu_en;
logic [WAPUTYPE-1:0] apu_type;
logic [WOP_CPU-1:0] apu_op;
logic [1:0] apu_lat;
logic [31:0] apu_operands [NARGS_CPU-1:0];
logic [NDSFLAGS_CPU-1:0] apu_flags;
logic [5:0] apu_waddr;
logic [2:0][5:0] apu_read_regs;
logic [2:0] apu_read_regs_valid;
logic [1:0][5:0] apu_write_regs;
logic [1:0] apu_write_regs_valid;
logic [WAPUTYPE-1:0] apu_flags_src;
logic apu_stall;
logic [2:0] fp_rnd_mode;
// Register Write Control
logic regfile_we_id;
logic regfile_alu_waddr_mux_sel;
// Data Memory Control
logic data_we_id;
logic [1:0] data_type_id;
logic data_sign_ext_id;
logic [1:0] data_reg_offset_id;
logic data_req_id;
logic data_load_event_id;
// hwloop signals
logic [N_HWLP_BITS-1:0] hwloop_regid, hwloop_regid_int;
logic [2:0] hwloop_we, hwloop_we_int;
logic hwloop_target_mux_sel;
logic hwloop_start_mux_sel;
logic hwloop_cnt_mux_sel;
logic [31:0] hwloop_target;
logic [31:0] hwloop_start, hwloop_start_int;
logic [31:0] hwloop_end;
logic [31:0] hwloop_cnt, hwloop_cnt_int;
logic hwloop_valid;
// CSR control
logic csr_access;
logic [1:0] csr_op;
logic csr_status;
logic prepost_useincr;
// Forwarding
logic [1:0] operand_a_fw_mux_sel;
logic [1:0] operand_b_fw_mux_sel;
logic [1:0] operand_c_fw_mux_sel;
logic [31:0] operand_a_fw_id;
logic [31:0] operand_b_fw_id;
logic [31:0] operand_c_fw_id;
logic [31:0] operand_b, operand_b_vec;
logic [31:0] alu_operand_a;
logic [31:0] alu_operand_b;
logic [31:0] alu_operand_c;
// Immediates for ID
logic [0:0] bmask_a_mux;
logic [1:0] bmask_b_mux;
logic alu_bmask_a_mux_sel;
logic alu_bmask_b_mux_sel;
logic [0:0] mult_imm_mux;
logic [ 4:0] bmask_a_id_imm;
logic [ 4:0] bmask_b_id_imm;
logic [ 4:0] bmask_a_id;
logic [ 4:0] bmask_b_id;
logic [ 1:0] imm_vec_ext_id;
logic [ 4:0] mult_imm_id;
logic [ 1:0] alu_vec_mode;
logic scalar_replication;
// Forwarding detection signals
logic reg_d_ex_is_reg_a_id;
logic reg_d_ex_is_reg_b_id;
logic reg_d_ex_is_reg_c_id;
logic reg_d_wb_is_reg_a_id;
logic reg_d_wb_is_reg_b_id;
logic reg_d_wb_is_reg_c_id;
logic reg_d_alu_is_reg_a_id;
logic reg_d_alu_is_reg_b_id;
logic reg_d_alu_is_reg_c_id;
assign instr = instr_rdata_i;
// immediate extraction and sign extension
assign imm_i_type = { {20 {instr[31]}}, instr[31:20] };
assign imm_iz_type = { 20'b0, instr[31:20] };
assign imm_s_type = { {20 {instr[31]}}, instr[31:25], instr[11:7] };
assign imm_sb_type = { {19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 };
assign imm_u_type = { instr[31:12], 12'b0 };
assign imm_uj_type = { {12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 };
// immediate for CSR manipulatin (zero extended)
assign imm_z_type = { 27'b0, instr[`REG_S1] };
assign imm_s2_type = { 27'b0, instr[24:20] };
assign imm_bi_type = { {27{instr[24]}}, instr[24:20] };
assign imm_s3_type = { 27'b0, instr[29:25] };
assign imm_vs_type = { {26 {instr[24]}}, instr[24:20], instr[25] };
assign imm_vu_type = { 26'b0, instr[24:20], instr[25] };
// same format as rS2 for shuffle needs, expands immediate
assign imm_shuffleb_type = {6'b0, instr[28:27], 6'b0, instr[24:23], 6'b0, instr[22:21], 6'b0, instr[20], instr[25]};
assign imm_shuffleh_type = {15'h0, instr[20], 15'h0, instr[25]};
// clipping immediate, uses a small barrel shifter to pre-process the
// immediate and an adder to subtract 1
// The end result is a mask that has 1's set in the lower part
// TODO: check if this can be shared with the bit-manipulation unit
assign imm_clip_type = (32'h1 << instr[24:20]) - 1;
//---------------------------------------------------------------------------
// source register selection regfile_fp_x=1 <=> REG_x is a FP-register
//---------------------------------------------------------------------------
assign regfile_addr_ra_id = {regfile_fp_a, instr[`REG_S1]};
assign regfile_addr_rb_id = {regfile_fp_b, instr[`REG_S2]};
// register C mux
always_comb
begin
unique case (regc_mux)
REGC_ZERO: regfile_addr_rc_id = '0;
REGC_RD: regfile_addr_rc_id = {regfile_fp_c, instr[`REG_D]};
REGC_S1: regfile_addr_rc_id = {regfile_fp_c, instr[`REG_S1]};
REGC_S4: regfile_addr_rc_id = {regfile_fp_c, instr[`REG_S4]};
default: regfile_addr_rc_id = '0;
endcase
end
//---------------------------------------------------------------------------
// destination registers regfile_fp_d=1 <=> REG_D is a FP-register
//---------------------------------------------------------------------------
assign regfile_waddr_id = {regfile_fp_d, instr[`REG_D]};
// Second Register Write Address Selection
// Used for prepost load/store and multiplier
assign regfile_alu_waddr_id = regfile_alu_waddr_mux_sel ?
regfile_waddr_id : regfile_addr_ra_id;
// Forwarding control signals
assign reg_d_ex_is_reg_a_id = (regfile_waddr_ex_o == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0);
assign reg_d_ex_is_reg_b_id = (regfile_waddr_ex_o == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0);
assign reg_d_ex_is_reg_c_id = (regfile_waddr_ex_o == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0);
assign reg_d_wb_is_reg_a_id = (regfile_waddr_wb_i == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0);
assign reg_d_wb_is_reg_b_id = (regfile_waddr_wb_i == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0);
assign reg_d_wb_is_reg_c_id = (regfile_waddr_wb_i == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0);
assign reg_d_alu_is_reg_a_id = (regfile_alu_waddr_fw_i == regfile_addr_ra_id) && (rega_used_dec == 1'b1) && (regfile_addr_ra_id != '0);
assign reg_d_alu_is_reg_b_id = (regfile_alu_waddr_fw_i == regfile_addr_rb_id) && (regb_used_dec == 1'b1) && (regfile_addr_rb_id != '0);
assign reg_d_alu_is_reg_c_id = (regfile_alu_waddr_fw_i == regfile_addr_rc_id) && (regc_used_dec == 1'b1) && (regfile_addr_rc_id != '0);
// kill instruction in the IF/ID stage by setting the instr_valid_id control
// signal to 0 for instructions that are done
assign clear_instr_valid_o = id_ready_o | halt_id | branch_taken_ex;
assign branch_taken_ex = branch_in_ex_o & branch_decision_i;
assign mult_en = mult_int_en | mult_dot_en;
///////////////////////////////////////////////
// _ ___ ___ ___ ___ ____ //
// | | | \ \ / / | / _ \ / _ \| _ \ //
// | |_| |\ \ /\ / /| | | | | | | | | |_) | //
// | _ | \ V V / | |__| |_| | |_| | __/ //
// |_| |_| \_/\_/ |_____\___/ \___/|_| //
// //
///////////////////////////////////////////////
// hwloop register id
assign hwloop_regid_int = instr[7]; // rd contains hwloop register id
// hwloop target mux
always_comb
begin
case (hwloop_target_mux_sel)
1'b0: hwloop_target = pc_id_i + {imm_iz_type[30:0], 1'b0};
1'b1: hwloop_target = pc_id_i + {imm_z_type[30:0], 1'b0};
endcase
end
// hwloop start mux
always_comb
begin
case (hwloop_start_mux_sel)
1'b0: hwloop_start_int = hwloop_target; // for PC + I imm
1'b1: hwloop_start_int = pc_if_i; // for next PC
endcase
end
// hwloop cnt mux
always_comb
begin : hwloop_cnt_mux
case (hwloop_cnt_mux_sel)
1'b0: hwloop_cnt_int = imm_iz_type;
1'b1: hwloop_cnt_int = operand_a_fw_id;
endcase;
end
// multiplex between access from instructions and access via CSR registers
assign hwloop_start = hwloop_we_int[0] ? hwloop_start_int : csr_hwlp_data_i;
assign hwloop_end = hwloop_we_int[1] ? hwloop_target : csr_hwlp_data_i;
assign hwloop_cnt = hwloop_we_int[2] ? hwloop_cnt_int : csr_hwlp_data_i;
assign hwloop_regid = (|hwloop_we_int) ? hwloop_regid_int : csr_hwlp_regid_i;
assign hwloop_we = (|hwloop_we_int) ? hwloop_we_int : csr_hwlp_we_i;
//////////////////////////////////////////////////////////////////
// _ _____ _ //
// | |_ _ _ __ ___ _ __ |_ _|_ _ _ __ __ _ ___| |_ //
// _ | | | | | '_ ` _ \| '_ \ | |/ _` | '__/ _` |/ _ \ __| //
// | |_| | |_| | | | | | | |_) | | | (_| | | | (_| | __/ |_ //
// \___/ \__,_|_| |_| |_| .__/ |_|\__,_|_| \__, |\___|\__| //
// |_| |___/ //
//////////////////////////////////////////////////////////////////
always_comb
begin : jump_target_mux
unique case (jump_target_mux_sel)
JT_JAL: jump_target = pc_id_i + imm_uj_type;
JT_COND: jump_target = pc_id_i + imm_sb_type;
// JALR: Cannot forward RS1, since the path is too long
JT_JALR: jump_target = regfile_data_ra_id + imm_i_type;
default: jump_target = regfile_data_ra_id + imm_i_type;
endcase
end
assign jump_target_o = jump_target;
////////////////////////////////////////////////////////
// ___ _ _ //
// / _ \ _ __ ___ _ __ __ _ _ __ __| | / \ //
// | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | / _ \ //
// | |_| | |_) | __/ | | (_| | | | | (_| | / ___ \ //
// \___/| .__/ \___|_| \__,_|_| |_|\__,_| /_/ \_\ //
// |_| //
////////////////////////////////////////////////////////
// ALU_Op_a Mux
always_comb
begin : alu_operand_a_mux
case (alu_op_a_mux_sel)
OP_A_REGA_OR_FWD: alu_operand_a = operand_a_fw_id;
OP_A_REGB_OR_FWD: alu_operand_a = operand_b_fw_id;
OP_A_REGC_OR_FWD: alu_operand_a = operand_c_fw_id;
OP_A_CURRPC: alu_operand_a = pc_id_i;
OP_A_IMM: alu_operand_a = imm_a;
default: alu_operand_a = operand_a_fw_id;
endcase; // case (alu_op_a_mux_sel)
end
always_comb
begin : immediate_a_mux
unique case (imm_a_mux_sel)
IMMA_Z: imm_a = imm_z_type;
IMMA_ZERO: imm_a = '0;
default: imm_a = '0;
endcase
end
// Operand a forwarding mux
always_comb
begin : operand_a_fw_mux
case (operand_a_fw_mux_sel)
SEL_FW_EX: operand_a_fw_id = regfile_alu_wdata_fw_i;
SEL_FW_WB: operand_a_fw_id = regfile_wdata_wb_i;
SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id;
default: operand_a_fw_id = regfile_data_ra_id;
endcase; // case (operand_a_fw_mux_sel)
end
//////////////////////////////////////////////////////
// ___ _ ____ //
// / _ \ _ __ ___ _ __ __ _ _ __ __| | | __ ) //
// | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | | _ \ //
// | |_| | |_) | __/ | | (_| | | | | (_| | | |_) | //
// \___/| .__/ \___|_| \__,_|_| |_|\__,_| |____/ //
// |_| //
//////////////////////////////////////////////////////
// Immediate Mux for operand B
// TODO: check if sign-extension stuff works well here, maybe able to save
// some area here
always_comb
begin : immediate_b_mux
unique case (imm_b_mux_sel)
IMMB_I: imm_b = imm_i_type;
IMMB_S: imm_b = imm_s_type;
IMMB_U: imm_b = imm_u_type;
IMMB_PCINCR: imm_b = (is_compressed_i && (~data_misaligned_i)) ? 32'h2 : 32'h4;
IMMB_S2: imm_b = imm_s2_type;
IMMB_BI: imm_b = imm_bi_type;
IMMB_S3: imm_b = imm_s3_type;
IMMB_VS: imm_b = imm_vs_type;
IMMB_VU: imm_b = imm_vu_type;
IMMB_SHUF: imm_b = imm_shuffle_type;
IMMB_CLIP: imm_b = {1'b0, imm_clip_type[31:1]};
default: imm_b = imm_i_type;
endcase
end
// ALU_Op_b Mux
always_comb
begin : alu_operand_b_mux
case (alu_op_b_mux_sel)
OP_B_REGA_OR_FWD: operand_b = operand_a_fw_id;
OP_B_REGB_OR_FWD: operand_b = operand_b_fw_id;
OP_B_REGC_OR_FWD: operand_b = operand_c_fw_id;
OP_B_IMM: operand_b = imm_b;
OP_B_BMASK: operand_b = $unsigned(operand_b_fw_id[4:0]);
default: operand_b = operand_b_fw_id;
endcase // case (alu_op_b_mux_sel)
end
// scalar replication for operand B and shuffle type
always_comb
begin
if (alu_vec_mode == VEC_MODE8) begin
operand_b_vec = {4{operand_b[7:0]}};
imm_shuffle_type = imm_shuffleb_type;
end else begin
operand_b_vec = {2{operand_b[15:0]}};
imm_shuffle_type = imm_shuffleh_type;
end
end
// choose normal or scalar replicated version of operand b
assign alu_operand_b = (scalar_replication == 1'b1) ? operand_b_vec : operand_b;
// Operand b forwarding mux
always_comb
begin : operand_b_fw_mux
case (operand_b_fw_mux_sel)
SEL_FW_EX: operand_b_fw_id = regfile_alu_wdata_fw_i;
SEL_FW_WB: operand_b_fw_id = regfile_wdata_wb_i;
SEL_REGFILE: operand_b_fw_id = regfile_data_rb_id;
default: operand_b_fw_id = regfile_data_rb_id;
endcase; // case (operand_b_fw_mux_sel)
end
//////////////////////////////////////////////////////
// ___ _ ____ //
// / _ \ _ __ ___ _ __ __ _ _ __ __| | / ___| //
// | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | | | //
// | |_| | |_) | __/ | | (_| | | | | (_| | | |___ //
// \___/| .__/ \___|_| \__,_|_| |_|\__,_| \____| //
// |_| //
//////////////////////////////////////////////////////
// ALU OP C Mux
always_comb
begin : alu_operand_c_mux
case (alu_op_c_mux_sel)
OP_C_REGC_OR_FWD: alu_operand_c = operand_c_fw_id;
OP_C_REGB_OR_FWD: alu_operand_c = operand_b_fw_id;
OP_C_JT: alu_operand_c = jump_target;
default: alu_operand_c = operand_c_fw_id;
endcase // case (alu_op_c_mux_sel)
end
// Operand c forwarding mux
always_comb
begin : operand_c_fw_mux
case (operand_c_fw_mux_sel)
SEL_FW_EX: operand_c_fw_id = regfile_alu_wdata_fw_i;
SEL_FW_WB: operand_c_fw_id = regfile_wdata_wb_i;
SEL_REGFILE: operand_c_fw_id = regfile_data_rc_id;
default: operand_c_fw_id = regfile_data_rc_id;
endcase; // case (operand_c_fw_mux_sel)
end
///////////////////////////////////////////////////////////////////////////
// ___ _ _ _ ___ ____ //
// |_ _|_ __ ___ _ __ ___ ___ __| (_) __ _| |_ ___ ___ |_ _| _ \ //
// | || '_ ` _ \| '_ ` _ \ / _ \/ _` | |/ _` | __/ _ \/ __| | || | | | //
// | || | | | | | | | | | | __/ (_| | | (_| | || __/\__ \ | || |_| | //
// |___|_| |_| |_|_| |_| |_|\___|\__,_|_|\__,_|\__\___||___/ |___|____/ //
// //
///////////////////////////////////////////////////////////////////////////
always_comb
begin
unique case (bmask_a_mux)
BMASK_A_ZERO: bmask_a_id_imm = '0;
BMASK_A_S3: bmask_a_id_imm = imm_s3_type[4:0];
default: bmask_a_id_imm = '0;
endcase
end
always_comb
begin
unique case (bmask_b_mux)
BMASK_B_ZERO: bmask_b_id_imm = '0;
BMASK_B_ONE: bmask_b_id_imm = 5'd1;
BMASK_B_S2: bmask_b_id_imm = imm_s2_type[4:0];
BMASK_B_S3: bmask_b_id_imm = imm_s3_type[4:0];
default: bmask_b_id_imm = '0;
endcase
end
always_comb
begin
unique case (alu_bmask_a_mux_sel)
BMASK_A_IMM: bmask_a_id = bmask_a_id_imm;
BMASK_A_REG: bmask_a_id = operand_b_fw_id[9:5];
default: bmask_a_id = bmask_a_id_imm;
endcase
end
always_comb
begin
unique case (alu_bmask_b_mux_sel)
BMASK_B_IMM: bmask_b_id = bmask_b_id_imm;
BMASK_B_REG: bmask_b_id = operand_b_fw_id[4:0];
default: bmask_b_id = bmask_b_id_imm;
endcase
end
assign imm_vec_ext_id = imm_vu_type[1:0];
always_comb
begin
unique case (mult_imm_mux)
MIMM_ZERO: mult_imm_id = '0;
MIMM_S3: mult_imm_id = imm_s3_type[4:0];
default: mult_imm_id = '0;
endcase
end
/////////////////////////////
// APU operand assignment //
/////////////////////////////
// read regs
generate
if (APU == 1) begin : apu_op_preparation
if (NARGS_CPU >= 1)
assign apu_operands[0] = alu_operand_a;
if (NARGS_CPU >= 2)
assign apu_operands[1] = alu_operand_b;
if (NARGS_CPU >= 3)
assign apu_operands[2] = alu_operand_c;
// write reg
assign apu_waddr = regfile_alu_waddr_id;
// flags
always_comb
begin
unique case (apu_flags_src)
APU_FLAGS_INT_MULT:
apu_flags = {7'h0 , mult_imm_id, mult_signed_mode, mult_sel_subword};
APU_FLAGS_DSP_MULT:
apu_flags = {13'h0, mult_dot_signed};
APU_FLAGS_FP:
if (FPU == 1) begin
if (fp_rnd_mode == 3'b111)
apu_flags = frm_i;
else
apu_flags = fp_rnd_mode;
end else
apu_flags = '0;
default:
apu_flags = '0;
endcase
end
// dependency checks
always_comb
begin
unique case (alu_op_a_mux_sel)
OP_A_REGA_OR_FWD: begin
apu_read_regs[0] = regfile_addr_ra_id;
apu_read_regs_valid [0] = 1'b1;
end // OP_A_REGA_OR_FWD:
OP_A_REGB_OR_FWD: begin
apu_read_regs[0] = regfile_addr_rb_id;
apu_read_regs_valid[0] = 1'b1;
end
default: begin
apu_read_regs[0] = regfile_addr_ra_id;
apu_read_regs_valid [0] = 1'b0;
end
endcase
end
always_comb
begin
unique case (alu_op_b_mux_sel)
OP_B_REGB_OR_FWD: begin
apu_read_regs[1] = regfile_addr_rb_id;
apu_read_regs_valid[1] = 1'b1;
end
OP_B_REGC_OR_FWD: begin
apu_read_regs[1] = regfile_addr_rc_id;
apu_read_regs_valid[1] = 1'b1;
end
default: begin
apu_read_regs[1] = regfile_addr_rb_id;
apu_read_regs_valid [1] = 1'b0;
end
endcase
end
always_comb
begin
unique case (alu_op_c_mux_sel)
OP_C_REGB_OR_FWD: begin
apu_read_regs[2] = regfile_addr_rb_id;
apu_read_regs_valid[2] = 1'b1;
end
OP_C_REGC_OR_FWD: begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid[2] = 1'b1;
end
default: begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid [2] = 1'b0;
end
endcase
end
assign apu_write_regs[0] = regfile_alu_waddr_id;
assign apu_write_regs_valid [0] = regfile_alu_we_id;
assign apu_write_regs[1] = regfile_waddr_id;
assign apu_write_regs_valid[1] = regfile_we_id;
assign apu_read_regs_o = apu_read_regs;
assign apu_read_regs_valid_o = apu_read_regs_valid;
assign apu_write_regs_o = apu_write_regs;
assign apu_write_regs_valid_o = apu_write_regs_valid;
end
else begin
for (genvar i=0;i<NARGS_CPU;i++)
assign apu_operands[i] = '0;
assign apu_waddr = '0;
assign apu_flags = '0;
assign apu_write_regs_o = '0;
assign apu_read_regs_o = '0;
assign apu_write_regs_valid_o = '0;
assign apu_read_regs_valid_o = '0;
end
endgenerate
assign apu_perf_dep_o = apu_stall;
// stall when we access the CSR after a multicycle APU instruction
assign csr_apu_stall = (csr_access & (apu_en_ex_o & (apu_lat_ex_o[1] == 1'b1) | apu_busy_i));
/////////////////////////////////////////////////////////
// ____ _____ ____ ___ ____ _____ _____ ____ ____ //
// | _ \| ____/ ___|_ _/ ___|_ _| ____| _ \/ ___| //
// | |_) | _|| | _ | |\___ \ | | | _| | |_) \___ \ //
// | _ <| |__| |_| || | ___) || | | |___| _ < ___) | //
// |_| \_\_____\____|___|____/ |_| |_____|_| \_\____/ //
// //
/////////////////////////////////////////////////////////
riscv_register_file
#(
.ADDR_WIDTH(6),
.FPU(FPU)
)
registers_i
(
.clk ( clk ),
.rst_n ( rst_n ),
.test_en_i ( test_en_i ),
.fregfile_disable_i ( fregfile_disable_i ),
// Read port a
.raddr_a_i ( regfile_addr_ra_id ),
.rdata_a_o ( regfile_data_ra_id ),
// Read port b
.raddr_b_i ( regfile_addr_rb_id ),
.rdata_b_o ( regfile_data_rb_id ),
// Read port c
.raddr_c_i ( (dbg_reg_rreq_i == 1'b0) ? regfile_addr_rc_id : dbg_reg_raddr_i),
.rdata_c_o ( regfile_data_rc_id ),
// Write port a
.waddr_a_i ( regfile_waddr_wb_i ),
.wdata_a_i ( regfile_wdata_wb_i ),
.we_a_i ( regfile_we_wb_i ),
// Write port b
.waddr_b_i ( (dbg_reg_wreq_i == 1'b0) ? regfile_alu_waddr_fw_i : dbg_reg_waddr_i ),
.wdata_b_i ( (dbg_reg_wreq_i == 1'b0) ? regfile_alu_wdata_fw_i : dbg_reg_wdata_i ),
.we_b_i ( (dbg_reg_wreq_i == 1'b0) ? regfile_alu_we_fw_i : 1'b1 )
);
assign dbg_reg_rdata_o = regfile_data_rc_id;
///////////////////////////////////////////////
// ____ _____ ____ ___ ____ _____ ____ //
// | _ \| ____/ ___/ _ \| _ \| ____| _ \ //
// | | | | _|| | | | | | | | | _| | |_) | //
// | |_| | |__| |__| |_| | |_| | |___| _ < //
// |____/|_____\____\___/|____/|_____|_| \_\ //
// //
///////////////////////////////////////////////
riscv_decoder
#(
.FPU ( FPU ),
.PULP_SECURE ( PULP_SECURE ),
.SHARED_FP ( SHARED_FP ),
.SHARED_DSP_MULT ( SHARED_DSP_MULT ),
.SHARED_INT_DIV ( SHARED_INT_DIV ),
.SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ),
.WAPUTYPE ( WAPUTYPE )
)
decoder_i
(
// controller related signals
.deassert_we_i ( deassert_we ),
.data_misaligned_i ( data_misaligned_i ),
.mult_multicycle_i ( mult_multicycle_i ),
.illegal_insn_o ( illegal_insn_dec ),
.ebrk_insn_o ( ebrk_insn ),
.mret_insn_o ( mret_insn_dec ),
.uret_insn_o ( uret_insn_dec ),
.ecall_insn_o ( ecall_insn_dec ),
.pipe_flush_o ( pipe_flush_dec ),
.rega_used_o ( rega_used_dec ),
.regb_used_o ( regb_used_dec ),
.regc_used_o ( regc_used_dec ),
.reg_fp_a_o ( regfile_fp_a ),
.reg_fp_b_o ( regfile_fp_b ),
.reg_fp_c_o ( regfile_fp_c ),
.reg_fp_d_o ( regfile_fp_d ),