CV32E40P does not implement all control and status registers specified in the RISC-V privileged specifications, but is limited to the registers that were needed for the PULP system. The reason for this is that we wanted to keep the footprint of the core as low as possible and avoid any overhead that we do not explicitly need.
Control and Status Register Map lists all implemented CSRs. To columns in Control and Status Register Map may require additional explanation:
The Parameter column identifies those CSRs that are dependent on the value of specific compile/synthesis parameters. If these parameters are not set as indicated in Control and Status Register Map then the associated CSR is not implemented. If the parameter column is empty then the associated CSR is always implemented.
The Privilege column indicates the access mode of a CSR. The first letter indicates the lowest privilege level required to access the CSR. Attempts to access a CSR with a higher privilege level than the core is currently running in will throw an illegal instruction exception. This is largely a moot point for the CV32E40P as it only supports machine and debug modes. The remaining letters indicate the read and/or write behavior of the CSR when accessed by the indicated or higher privilge level:
- RW: CSR is read-write. That is, CSR instructions (e.g. csrrw) may write any value and that value will be returned on a subsequent read (unless a side-effect causes the core to change the CSR value).
- RO: CSR is read-only. Writes by CSR instructions raise an illegal instruction exception.
Writes of a non-supported value to WLRL bitfields of a RW CSR do not result in an illegal instruction exception. The exact bitfield access types, e.g. WLRL or WARL, can be found in the RISC-V privileged specification.
Reads or writes to a CSR that is not implemented will result in an illegal instruction exception.
Control and Status Register Map| CSR Address | Name | Privilege | Parameter | Description |
|---|---|---|---|---|
| User CSRs | ||||
| 0x001 | fflags |
URW | FPU = 1 |
Floating-point accrued exceptions. |
| 0x002 | frm |
URW | FPU = 1 |
Floating-point dynamic rounding mode. |
| 0x003 | fcsr |
URW | FPU = 1 |
Floating-point control and status register. |
| 0xC00 | cycle |
URO | (HPM) Cycle Counter | |
| 0xC02 | instret |
URO | (HPM) Instructions-Retired Counter | |
| 0xC03 | hpmcounter3 |
URO | (HPM) Performance-Monitoring Counter 3 | |
| . | . | . | . | . |
| 0xC1F | hpmcounter31 |
URO | (HPM) Performance-Monitoring Counter 31 | |
| 0xC80 | cycleh |
URO | (HPM) Upper 32 Cycle Counter | |
| 0xC82 | instreth |
URO | (HPM) Upper 32 Instructions-Retired Counter | |
| 0xC83 | hpmcounterh3 |
URO | (HPM) Upper 32 Performance-Monitoring Counter 3 | |
| . | . | . | . | . |
| 0xC9F | hpmcounterh31 |
URO | (HPM) Upper 32 Performance-Monitoring Counter 31 | |
| User Custom CSR | s | |||
| 0x800 | lpstart0 |
URW | PULP_XPULP = 1 |
Hardware Loop 0 Start. |
| 0x801 | lpend0 |
URW | PULP_XPULP = 1 |
Hardware Loop 0 End. |
| 0x802 | lpcount0 |
URW | PULP_XPULP = 1 |
Hardware Loop 0 Counter. |
| 0x804 | lpstart1 |
URW | PULP_XPULP = 1 |
Hardware Loop 1 Start. |
| 0x805 | lpend1 |
URW | PULP_XPULP = 1 |
Hardware Loop 1 End. |
| 0x806 | lpcount1 |
URW | PULP_XPULP = 1 |
Hardware Loop 1 Counter. |
| 0xCC0 | uhartid |
URO | PULP_XPULP = 1 |
Hardware Thread ID |
| 0xCC1 | privlv |
URO | PULP_XPULP = 1 |
Privilege Level |
| Machine CSRs | ||||
| 0x300 | mstatus |
MRW | Machine Status | |
| 0x301 | misa |
MRW | Machine ISA | |
| 0x304 | mie |
MRW | Machine Interrupt Enable Register | |
| 0x305 | mtvec |
MRW | Machine Trap-Handler Base Address | |
| 0x320 | mcountinhibit |
MRW | (HPM) Machine Counter-Inhibit Register | |
| 0x323 | mhpmevent3 |
MRW | (HPM) Machine Performance-Monitoring Event Selector 3 | |
| . | . | . | . | |
| 0x33F | mhpmevent31 |
MRW | (HPM) Machine Performance-Monitoring Event Selector 31 | |
| 0x340 | mscratch |
MRW | Machine Scratch | |
| 0x341 | mepc |
MRW | Machine Exception Program Counter | |
| 0x342 | mcause |
MRW | Machine Trap Cause | |
| 0x343 | mtval |
MRW | Machine Trap Value | |
| 0x344 | mip |
MRW | Machine Interrupt Pending Register | |
| 0x7A0 | tselect |
MRW | Trigger Select Register | |
| 0x7A1 | tdata1 |
MRW | Trigger Data Register 1 | |
| 0x7A2 | tdata2 |
MRW | Trigger Data Register 2 | |
| 0x7A3 | tdata3 |
MRW | Trigger Data Register 3 | |
| 0x7A4 | tinfo |
MRO | Trigger Info | |
| 0x7A8 | mcontext |
MRW | Machine Context Register | |
| 0x7AA | scontext |
MRW | Machine Context Register | |
| 0x7B0 | dcsr |
DRW | Debug Control and Status | |
| 0x7B1 | dpc |
DRW | Debug PC | |
| 0x7B2 | dscratch0 |
DRW | Debug Scratch Register 0 | |
| 0x7B3 | dscratch1 |
DRW | Debug Scratch Register 1 | |
| 0xB00 | mcycle |
MRW | (HPM) Machine Cycle Counter | |
| 0xB02 | minstret |
MRW | (HPM) Machine Instructions-Retired Counter | |
| 0xB03 | mhpmcounter3 |
MRW | (HPM) Machine Performance-Monitoring Counter 3 | |
| . | . | . | . | |
| 0xB1F | mhpmcounter31 |
MRW | (HPM) Machine Performance-Monitoring Counter 31 | |
| 0xB80 | mcycleh |
MRW | (HPM) Upper 32 Machine Cycle Counter | |
| 0xB82 | minstreth |
MRW | (HPM) Upper 32 Machine Instructions-Retired Counter | |
| 0xB83 | mhpmcounterh3 |
MRW | (HPM) Upper 32 Machine Performance-Monitoring Counter 3 | |
| . | . | . | . | |
| 0xB9F | mhpmcounterh31 |
MRW | (HPM) Upper 32 Machine Performance-Monitoring Counter 31 | |
| 0xF11 | mvendorid |
MRO | Machine Vendor ID | |
| 0xF12 | marchid |
MRO | Machine Architecture ID | |
| 0xF13 | mimpid |
MRO | Machine Implementation ID | |
| 0xF14 | mhartid |
MRO | Hardware Thread ID |
USER
What follows is a detailed definition of each of the CSRs listed above. The Mode column defines the access mode behavior of each bit field when accessed by the privilege level specified in Control and Status Register Map (or a higher privilege level):
- RO: read-only fields are not affect by CSR write instructions. Such fields either return a fixed value, or a value determined by the operation of the core.
- RW: read/write fields store the value written by CSR writes. Subsequent reads return either the previously written value or a value determined by the operation of the core.
CSR Address: 0x001 (only present if FPU = 1)
Reset Value: 0x0000_0000
| Bit # | Mode | Description |
|---|---|---|
| 31:5 | RO | Writes are ignored; reads return 0. |
| 4 | RW | NV- Invalid Operation |
| 3 | RW | DZ - Divide by Zero |
| 2 | RW | OF - Overflow |
| 1 | RW | UF - Underflow |
| 0 | RW | NX - Inexact |
CSR Address: 0x002 (only present if FPU = 1)
Reset Value: 0x0000_0000
| Bit # | Mode | Description |
|---|---|---|
| 31:3 | RO | Writes are ignored; reads return 0. |
| 2:0 | RW | Rounding mode. 000 = RNE, 001 = RTZ, 010 = RDN, 011 = RUP, 100 = RMM 101 = Invalid, 110 = Invalid, 111 = DYN. |
CSR Address: 0x003 (only present if FPU = 1)
Reset Value: 0x0000_0000
| Bit # | Mode | Description |
|---|---|---|
| 31:8 | RO | Reserved. Writes are ignored; reads return 0. |
| 7:5 | RW | Rounding Mode (frm) |
| 4:0 | RW | Accrued Exceptions (fflags) |
CSR Address: 0x800/0x804 (only present if PULP_XPULP = 1)
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RW | Start Address of the HWLoop 0/1. |
CSR Address: 0x801/0x805 (only present if PULP_XPULP = 1)
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RW | End Address of the HWLoop 0/1. |
CSR Address: 0x802/0x806 (only present if PULP_XPULP = 1)
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RW | Number of iteration of HWLoop 0/1. |
CSR Address: 0xCC1 (only present if PULP_XPULP = 1)
Reset Value: 0x0000_0003
PRIVLV| Bit # | Mode | Description |
|---|---|---|
| 31:2 | RO | Reads as 0. |
| 1:0 | RO | Current Privilege Level. 11 = Machine, 10 = Hypervisor, 01 = Supervisor, 00 = User. CV32E40P only supports Machine mode. |
CSR Address: 0xCC0 (only present if PULP_XPULP = 1)
Reset Value: Defined
UHARTID| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RO | Hardware Thread ID hart_id_i, see core-integration |
Similar to mhartid the uhartid provides the Hardware Thread ID. It differs from mhartid only in the required privilege level. On CV32E40P, as it is a machine mode only implementation, this difference is not noticeable.
CSR Address: 0x300
Reset Value: 0x0000_1800
| Bit # | Mode | Description |
|---|---|---|
| 31:18 | RO | Reserved, hardwired to 0 |
| 17 | RO | MPRV: hardwired to 0 |
| 16:13 | RO | Unimplemented, hardwired to 0 |
| 12:11 | RO | MPP: Machine Previous Priviledge mode, hardwired to 11 when the user mode is not enabled. |
| 10:8 | RO | Unimplemented, hardwired to 0 |
| 7 | RO | Previous Machine Interrupt Enable: When an exception is encountered, MPIE will be set to MIE. When the mret instruction is executed, the value of MPIE will be stored to MIE. |
| 6:5 | RO | Unimplemented, hardwired to 0 |
| 4 | RO | Previous User Interrupt Enable: If user mode is enabled, when an exception is encountered, UPIE will be set to UIE. When the uret instruction is executed, the value of UPIE will be stored to UIE. |
| 3 | RW | Machine Interrupt Enable: If you want to enable interrupt handling in your exception handler, set the Interrupt Enable MIE to 1 inside your handler code. |
| 2:1 | RO | Unimplemented, hardwired to 0 |
| 0 | RO | User Interrupt Enable: If you want to enable user level interrupt handling in your exception handler, set the Interrupt Enable UIE to 1 inside your handler code. |
USER
CSR Address: 0x000
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 4 | RW | Previous User Interrupt Enable: If user mode is enabled, when an exception is encountered, UPIE will be set to UIE. When the uret instruction is executed, the value of UPIE will be stored to UIE. |
| 0 | RW | User Interrupt Enable: If you want to enable user level interrupt handling in your exception handler, set the Interrupt Enable UIE to 1 inside your handler code. |
CSR Address: 0x301
Reset Value: defined
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:30 | RO (0x1) |
|
| 29:26 | RO (0x0) | (Reserved). |
| 25 | RO (0x0) | Z (Reserved). Read-only; writes are ignored. |
| 24 | RO (0x0) | Y (Reserved). |
| 23 | RO | X (Non-standard extensions present). |
| 22 | RO (0x0) | W (Reserved). |
| 21 | RO (0x0) | V (Tentatively reserved for Vector extension). |
| 20 | RO (0x0) | U (User mode implemented). |
| 19 | RO (0x0) | T (Tentatively reserved for Transactional Memory extension). |
| 18 | RO (0x0) | S (Supervisor mode implemented). |
| 17 | RO (0x0) | R (Reserved). |
| 16 | RO (0x0) | Q (Quad-precision floating-point extension). |
| 15 | RO (0x0) | P (Tentatively reserved for Packed-SIMD extension). |
| 14 | RO (0x0) | O (Reserved). |
| 13 | RO (0x0) | N (User-level interrupts supported). |
| 12 | RO (0x1) | M (Integer Multiply/Divide extension). |
| 11 | RO (0x0) | L (Tentatively reserved for Decimal Floating-Point extension). |
| 10 | RO (0x0) | K (Reserved). |
| 9 | RO (0x0) | J (Tentatively reserved for Dynamically Translated Languages extension). |
| 8 | RO (0x1) | I (RV32I/64I/128I base ISA). |
| 7 | RO (0x0) | H (Hypervisor extension). |
| 6 | RO (0x0) | G (Additional standard extensions present). |
| 5 | RO | F (Single-precision floating-point extension). |
| 4 | RO (0x0) | E (RV32E base ISA). |
| 3 | RO (0x0) | D (Double-precision floating-point extension). |
| 2 | RO (0x1) | C (Compressed extension). |
| 1 | RO (0x0) | B (Tentatively reserved for Bit-Manipulation extension). |
| 0 | RO (0x0) | A (Atomic extension). |
All bitfields in the misa CSR read as 0 except for the following:
- C = 1
- F = 1 if
FPU= 1 andPULP_ZFINX= 0 - I = 1
- M = 1
- X = 1 if
PULP_XPULP= 1 orPULP_CLUSTER= 1 - MXL = 1 (i.e. XLEN = 32)
CSR Address: 0x304
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:16 | RW | Machine Fast Interrupt Enables: Set bit x to enable interrupt irq_i[x]. |
| 11 | RW | Machine External Interrupt Enable (MEIE): If set, irq_i[11] is enabled. |
| 7 | RW | Machine Timer Interrupt Enable (MTIE): If set, irq_i[7] is enabled. |
| 3 | RW | Machine Software Interrupt Enable (MSIE): if set, irq_i[3] is enabled. |
CSR Address: 0x305
Reset Value: Defined
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31 : 8 |
|
BASE[31:8]: The trap-handler base address, always aligned to 256 bytes. |
|
|
BASE[7:2]: The trap-handler base address, always aligned to 256 bytes, i.e., mtvec[7:2] is always set to 0. |
|
|
MODE[1]: always 0 |
|
|
MODE[0]: 0 = direct mode, 1 = vectored mode. |
The initial value of mtvec is equal to {mtvec_addr_i[31:8], 6'b0, 2'b01}.
When an exception or an interrupt is encountered, the core jumps to the corresponding handler using the content of the MTVEC[31:8] as base address. Only 8-byte aligned addresses are allowed. Both direct mode and vectored mode are supported.
USER
CSR Address: 0x306
Reset Value: 0x0000_0000
Detailed:
Each bit in the machine counter-enable register allows the associated read-only unprivileged shadow performance register to be read from user mode. If the bit is clear an attempt to read the register in user mode will trigger an illegal instruction exception.
| Bit# | Mode | Description |
|---|---|---|
| 31:4 | RW | Dependent on number of counters implemented in design parameter |
| 3 | RW | selectors: hpmcounter3 enable for user mode |
| 2 | RW | instret enable for user mode |
| 1 | RO | 0 |
| 0 | RW | cycle enable for user mode |
CSR Address: 0x320
Reset Value: 0x0000_000D
The performance counter inhibit control register. The default value is to inihibit counters out of reset. The bit returns a read value of 0 for non implemented counters. This reset value shows the result using the default number of performance counters to be 1.
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:4 | RW | Dependent on number of counters implemented in design parameter |
| 3 | RW | selectors: mhpmcounter3 inhibit |
| 2 | RW | minstret inhibit |
| 1 | RO | 0 |
| 0 | RW | mcycle inhibit |
CSR Address: 0x323 - 0x33F
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:16 | RO | 0 |
| 15:0 | RW | selectors: Each bit represent a unique event to count |
The event selector fields are further described in Performance Counters section. Non implemented counters always return a read value of 0.
CSR Address: 0x340
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RW | Scratch value |
CSR Address: 0x341
Reset Value: 0x0000_0000
| Bit # | Mode | Description |
|---|---|---|
| 31:1 | RW | Machine Expection Program Counter 31:1 |
|
R0 | Always 0 |
When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. When a mret instruction is executed, the value from MEPC replaces the current program counter.
CSR Address: 0x342
Reset Value: 0x0000_0000
| Bit # | Mode | Description |
|---|---|---|
| 31 |
|
Interrupt: This bit is set when the exception was triggered by an interrupt. |
| 30:5 |
|
Always 0 |
| 4:0 |
|
Exception Code (See note below) |
NOTE: software accesses to mcause[4:0] must be sensitive to the WLRL field specification of this CSR. For example, when mcause[31] is set, writing 0x1 to mcause[1] (Supervisor software interrupt) will result in UNDEFINED behavior.
CSR Address: 0x343
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RO (0) | Writes are ignored; reads return 0. |
CSR Address: 0x344
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:16 | RO | Machine Fast Interrupts Pending: If bit x is set, interrupt irq_i[x] is pending. |
| 11 | RO | Machine External Interrupt Pending (MEIP): If set, irq_i[11] is pending. |
| 7 | RO | Machine Timer Interrupt Pending (MTIP): If set, irq_i[7] is pending. |
| 3 | RO | Machine Software Interrupt Pending (MSIP): if set, irq_i[3] is pending. |
CSR Address: 0x7A0
Reset Value: 0x0000_0000
Accessible in Debug Mode or M-Mode.
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RO | CV32E40P implements a single trigger, therefore this register will always read as zero |
CSR Address: 0x7A1
Reset Value: 0x2800_1040
Accessible in Debug Mode or M-Mode. Since native triggers are not supported, writes to this register from M-Mode will be ignored.
Note
CV32E40P only implements one type of trigger, Match Control. Most fields of this register will read as a fixed value to reflect the single mode that is supported, in particular, instruction address match as described in the Debug Specification 0.13.2 section 5.2.2 & 5.2.9. The type, dmode, hit, select, timing, sizelo, action, chain, match, m, s, u, store and load bitfields of this CSR, which are marked as R/W in Debug Specification 0.13.2, are therefore implemented as WARL bitfields (corresponding to how these bitfields will be specified in the forthcoming Debug Specification 0.14.0).
| Bit# | Mode | Description |
|---|---|---|
| 31:28 | RO (0x2) | type: 2 = Address/Data match trigger type. |
| 27 | RO (0x1) | dmode: 1 = Only debug mode can write tdata registers |
| 26:21 | RO (0x0) | maskmax: 0 = Only exact matching supported. |
| 20 | RO (0x0) | hit: 0 = Hit indication not supported. |
| 19 | RO (0x0) | select: 0 = Only address matching is supported. |
| 18 | RO (0x0) | timing: 0 = Break before the instruction at the specified address. |
| 17:16 | RO (0x0) | sizelo: 0 = Match accesses of any size. |
| 15:12 | RO (0x1) | action: 1 = Enter debug mode on match. |
| 11 | RO (0x0) | chain: 0 = Chaining not supported. |
| 10:7 | RO (0x0) | match: 0 = Match the whole address. |
| 6 | RO (0x1) | m: 1 = Match in M-Mode. |
| 5 | RO (0x0) | zero. |
| 4 | RO (0x0) | s: 0 = S-Mode not supported. |
| 3 | RO (0x0) | u: 0 = U-Mode not supported. |
| 2 | RW | execute: Enable matching on instruction address. |
| 1 | RO (0x0) | store: 0 = Store address / data matching not supported. |
| 0 | RO (0x0) | load: 0 = Load address / data matching not supported. |
CSR Address: 0x7A2
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | data |
Accessible in Debug Mode or M-Mode. Since native triggers are not supported, writes to this register from M-Mode will be ignored. This register stores the instruction address to match against for a breakpoint trigger.
CSR Address: 0x7A3
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RO | 0 |
Accessible in Debug Mode or M-Mode. CV32E40P does not support the features requiring this register. Writes are ignored and reads will always return zero.
CSR Address: 0x7A4
Reset Value: 0x0000_0004
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:16 | RO (0x0) | 0 |
| 15:0 | RO (0x4) | info. Only type 2 is supported. |
The info field contains one bit for each possible type enumerated in tdata1. Bit N corresponds to type N. If the bit is set, then that type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1.
Accessible in Debug Mode or M-Mode.
CSR Address: 0x7A8
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RO | 0 |
Accessible in Debug Mode or M-Mode. CV32E40P does not support the features requiring this register. Writes are ignored and reads will always return zero.
CSR Address: 0x7AA
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RO | 0 |
Accessible in Debug Mode or M-Mode. CV32E40P does not support the features requiring this register. Writes are ignored and reads will always return zero.
CSR Address: 0x7B0
Reset Value: 0x4000_0003
Note
The ebreaks, ebreaku and prv bitfields of this CSR are marked as R/W in Debug Specification 0.13.2. However, as CV32E40P only supports machine mode, these bitfields are implemented as WARL bitfields (corresponding to how these bitfields will be specified in the forthcoming Debug Specification 0.14.0).
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:28 | RO (0x4) | xdebugver: returns 4 - External debug support exists as it is described in this document. |
| 27:16 | RO (0x0) | Reserved |
| 15 | RW | ebreakm |
| 14 | RO (0x0) | Reserved |
| 13 | RO (0x0) | ebreaks. Always 0. |
| 12 | RO (0x0) | ebreaku. Always 0. |
| 11 | RW | stepie |
| 10 | RO (0x0) | stopcount. Always 0. |
| 9 | RO (0x0) | stoptime. Always 0. |
| 8:6 | RO | cause |
| 5 | RO (0x0) | Reserved |
| 4 | RO (0x0) | mprven. Always 0. |
| 3 | RO (0x0) | nmip. Always 0. |
| 2 | RW | step |
| 1:0 | RO (0x3) | prv: returns the current priviledge mode |
CSR Address: 0x7B1
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:1 | RO | zero |
| 0 | RO | DPC |
When the core enters in Debug Mode, DPC contains the virtual address of the next instruction to be executed.
CSR Address: 0x7B2/0x7B3
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RW | DSCRATCH0/1 |
CSR Address: 0xB00
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | The lower 32 bits of the 64 bit machine mode cycle counter. |
CSR Address: 0xB02
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | The lower 32 bits of the 64 bit machine mode instruction retired counter. |
CSR Address: 0xB03 - 0xB1F
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | Machine performance-monitoring counter |
The lower 32 bits of the 64 bit machine performance-monitoring counter(s). The number of machine performance-monitoring counters is determined by the parameter NUM_MHPMCOUNTERS with a range from 0 to 29 (default value of 1). Non implemented counters always return a read value of 0.
CSR Address: 0xB80
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | The upper 32 bits of the 64 bit machine mode cycle counter. |
CSR Address: 0xB82
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | The upper 32 bits of the 64 bit machine mode instruction retired counter. |
CSR Address: 0xB83 - 0xB9F
Reset Value: 0x0000_0000
Detailed:
| Bit# | Mode | Description |
|---|---|---|
| 31:0 | RW | Machine performance-monitoring counter |
The upper 32 bits of the 64 bit machine performance-monitoring counter(s). The number of machine performance-monitoring counters is determined by the parameter NUM_MHPMCOUNTERS with a range from 0 to 29 (default value of 1). Non implemented counters always return a read value of 0.
CSR Address: 0xF11
Reset Value: 0x0000_0602
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:7 | RO | 0xC. Number of continuation codes in JEDEC manufacturer ID. |
| 6:0 | RO | 0x2. Final byte of JEDEC manufacturer ID, discarding the parity bit. |
The mvendorid encodes the OpenHW JEDEC Manufacturer ID, which is 2 decimal (bank 13).
CSR Address: 0xF12
Reset Value: 0x0000_0004
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RO | Machine Architecture ID of CV32E40P is 4 |
CSR Address: 0xF13
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RO | Reads return 0. |
CSR Address: 0xF14
Reset Value: Defined
| Bit # | Mode | Description |
|---|---|---|
| 31:0 | RO | Hardware Thread ID hart_id_i, see core-integration |
USER
CSR Address: 0x005
| Bit # | Mode | Description |
|---|---|---|
| 31 : 2 |
|
BASE: The trap-handler base address, always aligned to 256 bytes, i.e., utvec[7:2] is always set to 0. |
|
|
MODE[1]: Always 0 |
|
|
MODE[0]: 0 = direct mode, 1 = vectored mode. |
When an exception is encountered in user-mode, the core jumps to the corresponding handler using the content of the UTVEC[31:8] as base address. Only 8-byte aligned addresses are allowed. Both direct mode and vectored mode are supported.
CSR Address: 0x041
Reset Value: 0x0000_0000
| 31 | 30: 0 |
|---|---|
| UEPC |
When an exception is encountered in user mode, the current program counter is saved in UEPC, and the core jumps to the exception address. When a uret instruction is executed, the value from UEPC replaces the current program counter.
CSR Address: 0x042
Reset Value: 0x0000_0000
Detailed:
| Bit # | Mode | Description |
|---|---|---|
| 31 | RW | Interrupt: This bit is set when the exception was triggered by an interrupt. |
| 30:5 |
|
Always 0 |
| 4:0 |
|
Exception Code (See note below) |
NOTE: software accesses to ucause[4:0] must be sensitive to the WLRL field specification of this CSR. For example, when ucause[31] is set, writing 0x1 to ucause[1] (Supervisor software interrupt) will result in UNDEFINED behavior.
PMP
CSR Address: 0x3A{0,1,2,3}
Reset Value: 0x0000_0000
| 31 : 0 |
|---|
| PMPCFGx |
If the PMP is enabled, these four registers contain the configuration of the PMP as specified by the official privileged spec 1.10.
CSR Address: 0x3B{0x0, 0x1, …. 0xF}
Reset Value: 0x0000_0000
| 31 : 0 |
|---|
| PMPADDRx |
If the PMP is enabled, these sixteen registers contain the addresses of the PMP as specified by the official privileged spec 1.10.
CSR Address: 0xC00
Reset Value: 0x0000_0000
Detailed:
| Bit# | R/W | Description |
|---|---|---|
| 31:0 | R | 0 |
Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode cycle counter.
CSR Address: 0xC02
Reset Value: 0x0000_0000
Detailed:
| Bit# | R/W | Description |
|---|---|---|
| 31:0 | R | 0 |
Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode instruction retired counter.
CSR Address: 0xC03 - 0xC1F
Reset Value: 0x0000_0000
Detailed:
| Bit# | R/W | Description |
|---|---|---|
| 31:0 | R | 0 |
Read-only unprivileged shadow of the lower 32 bits of the 64 bit machine mode performance counter. Non implemented counters always return a read value of 0.
CSR Address: 0xC80
Reset Value: 0x0000_0000
Detailed:
| Bit# | R/W | Description |
|---|---|---|
| 31:0 | R | 0 |
Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode cycle counter.
CSR Address: 0xC82
Reset Value: 0x0000_0000
Detailed:
| Bit# | R/W | Description |
|---|---|---|
| 31:0 | R | 0 |
Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode instruction retired counter.
CSR Address: 0xC83 - 0xC9F
Reset Value: 0x0000_0000
Detailed:
| Bit# | R/W | Description |
|---|---|---|
| 31:0 | R | 0 |
Read-only unprivileged shadow of the upper 32 bits of the 64 bit machine mode performance counter. Non implemented counters always return a read value of 0.