- ALU: Arithmetic/Logic Unit
- ASIC: Application-Specific Integrated Circuit
- Byte: 8-bit data item
- CPU: Central Processing Unit, processor
- CSR: Control and Status Register
- Custom extension: Non-Standard extension to the RISC-V base instruction set (RISC-V Instruction Set Manual, Volume I: User-Level ISA)
- EXE: Instruction Execute
- FPGA: Field Programmable Gate Array
- FPU: Floating Point Unit
- Halfword: 16-bit data item
- Halfword aligned address: An address is halfword aligned if it is divisible by 2
- ID: Instruction Decode
- IF: Instruction Fetch (
instruction-fetch) - ISA: Instruction Set Architecture
- KGE: kilo gate equivalents (NAND2)
- LSU: Load Store Unit (
load-store-unit) - M-Mode: Machine Mode (RISC-V Instruction Set Manual, Volume II: Privileged Architecture)
- NMI: Non-Maskable Interrupt
- OBI: Open Bus Interface
- PC: Program Counter
- PMA: Physical Memory Attribution
- RV32C: RISC-V Compressed (C extension)
- RV32F: RISC-V Floating Point (F extension)
- SIMD: Single Instruction/Multiple Data
- Standard extension: Standard extension to the RISC-V base instruction set (RISC-V Instruction Set Manual, Volume I: User-Level ISA)
- WARL: Write Any Values, Reads Legal Values
- WB: Write Back of instruction results
- WLRL: Write/Read Only Legal Values
- Word: 32-bit data item
- Word aligned address: An address is word aligned if it is divisible by 4
- WPRI: Reserved Writes Preserve Values, Reads Ignore Values