Closed
Description
Our co-simulation framework found that the mstatus.sd field does not update immediately after mstatus.fs field is dirty.
In the following test case, we set mstatus.fs field to initial(0b01), and then execute a float-point instruction. After the float-point instruction, we read the value in mastatus. We found that cva6 successfully sets fs to dirty while sd is still zero.
[spike] core 0: 0x0000000080000148 (0x300022f3) csrr t0, mstatus
[cva6] 615ns 600 M 0000000080000148 0 300022f3 csrr t0, mstatus
[spike] core 0: 0x000000008000014c (0x00002517) auipc a0, 0x2
[cva6] 617ns 602 M 000000008000014c 0 00002517 auipc a0, 0x2
[spike] core 0: 0x0000000080000150 (0xebc53487) fld fs1, -324(a0)
[cva6] 651ns 636 M 0000000080000150 0 ebc53487 fld fs1, -324(a0)
[spike] core 0: 0x0000000080000154 (0x300022f3) csrr t0, mstatus
[error] WDATA SIM 8000000a00006080, DUT 0000000a00006080
[error] check board clear 5 error
According to riscv-privileged specification:
The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory.