- François Leduc-Primeau, Polytechnique Montreal
- Mike Aronson, Rumble Dev
- Duncan Bees, OpenHW
PolyMtl is providing 1 Master’s student supervised by Prof. Leduc-Primeau and funded by Empaiot. In addition, Empaiot and RumbleDev are providing engineering support as specified in the table below.
| Item | Resource | Rough Timespan |
|---|---|---|
| Polara daughter board schematics | RumbleDev, PolyMtl | Jan. 8, 2024 – Mar. 4, 2024 |
| Development of Chipset on Genesys2 | PolyMtl | Jan. 8 2024 – May 3, 2024 |
| Polara daughter board layout | Empaiot | Mar. 4, 2024 – Apr. 1, 2024 |
| Polara daughter board manufacture | Empaiot | Apr 1, 2024 – Apr. 22, 2024 |
| Bring up of Polara chip/board | PolyMtl | May 8, 2024 – June 5, 2024 |
| User manual for DevKit and Interface | PolyMtl | May 8, 2024 – June 12, 2024 |
| Use Case development and testing of Polara DevKit | PolyMtl | June 5, 2024 – July 31, 2024 |
| Document results of testing | PolyMtl | July 31, 2024 – Aug. 7, 2024 |
| Document | License | Leader | Rough Timeframe |
|---|---|---|---|
| DevKit schematic | Solderpad 2.1 | F. Leduc-Primeau | Feb. 2024 |
| DevKit layout | Solderpad 2.1 | Mike Aronson | Apr. 2024 |
| DevKits manufactured | n/a | Alfred Shiu | End of April 2024 |
| Bring up software | Apache 2.0 | F. Leduc-Primeau | Start of May 2024 |
| Use case test software (baremetal for VEC testing) | Apache 2.0 | F. Leduc-Primeau | Aug. 2024 |
| SMP linux on CVA6 but not for VEC | GPL | F. Leduc-Primeau | Aug. 2024 |
| Dependency | Explanation |
|---|---|
| Polara tapeout | Silicon expected back May 7, 2024 |
| Polara packaging | Packaged chips expected May 7, 2024 (CMC delivery date includes packaging) |
| Polara FPGA testing | Currently the Polara chip is emulated in FPGA and is (almost) running SMP Linux. Software running on FPGA will be able to be ported to the DevKit. |
| Check power supply capabilities of Genesys2 board | If Genesys board can provide enough power, may not need to bring power supply directly to the development board. |
The project should be reviewed in either the OpenHW HW TG or the Interconnect TG.
In addition to engineering resources above, management and support resources are as follows.
- Project Manager for hardware development: Mike Aronson
- Project Manager for software integration: Francois Leduc-Primeau
- OpenPiton support: Jonathan Balkind
- Hardware - Solderpad 2.1
- Software - Apache 2.0
Not applicable
| Repo | License | Explanation |
|---|---|---|
core-v-polara-devboard |
Solderpad | Board schematics and layout, User manual, FPGA RTL code for the chipset, FPGA image for the Genesys2 “chipset”, Low level software (demo level) |
linux |
Existing OpenHW linux repository will be used to host the linux distribution for Polara. |
The software and RTL code generated by this project will be distributed on Github.
Although this project does not endeavour to distribute boards to “general public” like the CORE-V MCU DevKit, limited availability of boards to OpenHW Group members who would commit to provide technical feedback is likely available on a cost recovery basis. A rough estimate of the costs per board is as follows: Polara packaging cost: 150 USD (source: rough estimate of 1500 USD for 10 parts from Hugh Pollitt-Smith) Board fabrication: approx. 10 USD (to be confirmed with Empaiot) Board BOM (excluding Polara): FMC connector is about 20-30 USD, and we can budget another 10 USD for the rest of the parts. Polara socket (17x17, 208 pins, low insertion force) ~20USD. Adding a socket for the Polara package simplifies the logistic since in that case PCB parts can be mounted before Polara is received, and boards can be distributed separately from the Polara chip itself without requiring users to do soldering.
A cutoff date for expression of interest will be communicated to the TWG as soon as established.
| Risk | Impact | Mitigation |
|---|---|---|
| Polara doesn’t work | Severe | Identify the issue and consider a second fabrication run. |
| Devboard errors cause need for respin | Moderate | Fix PCB design error and fabricate boards again. |
| Genesys2 availability insufficient | Moderate | Port the Chipset project to a different board. |