fix aarch and cpu name of riscv port

make/autoconf/platform.m4

@@ -128,7 +128,7 @@ AC_DEFUN([PLATFORM_EXTRACT_VARS_FROM_CPU],
       ;;
     riscv64)
       VAR_CPU=riscv64
-      VAR_CPU_ARCH=riscv64
+      VAR_CPU_ARCH=riscv
       VAR_CPU_BITS=64
       VAR_CPU_ENDIAN=little
       ;;
@@ -561,20 +561,18 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER],
     HOTSPOT_$1_CPU_DEFINE=PPC64
   elif test "x$OPENJDK_$1_CPU" = xppc64le; then
     HOTSPOT_$1_CPU_DEFINE=PPC64
+  elif test "x$OPENJDK_$1_CPU" = xriscv64; then
+    HOTSPOT_$1_CPU_DEFINE=RISCV64
 
   # The cpu defines below are for zero, we don't support them directly.
   elif test "x$OPENJDK_$1_CPU" = xsparc; then
     HOTSPOT_$1_CPU_DEFINE=SPARC
   elif test "x$OPENJDK_$1_CPU" = xppc; then
     HOTSPOT_$1_CPU_DEFINE=PPC32
-  elif test "x$OPENJDK_$1_CPU" = xriscv64; then
-    HOTSPOT_$1_CPU_DEFINE=RISCV64
   elif test "x$OPENJDK_$1_CPU" = xs390; then
     HOTSPOT_$1_CPU_DEFINE=S390
   elif test "x$OPENJDK_$1_CPU" = xs390x; then
     HOTSPOT_$1_CPU_DEFINE=S390
-  elif test "x$OPENJDK_$1_CPU" = xriscv64; then
-    HOTSPOT_$1_CPU_DEFINE=RISCV
   elif test "x$OPENJDK_$1_CPU" != x; then
     HOTSPOT_$1_CPU_DEFINE=$(echo $OPENJDK_$1_CPU | tr a-z A-Z)
   fi

make/hotspot/gensrc/GensrcAdlc.gmk

@@ -146,7 +146,7 @@ ifeq ($(call check-jvm-feature, compiler2), true)
     )))
   endif
 
-  ifeq ($(HOTSPOT_TARGET_CPU_ARCH), riscv64)
+  ifeq ($(HOTSPOT_TARGET_CPU_ARCH), riscv)
     AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \
         $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_CPU_ARCH)_vext.ad \
     )))

src/hotspot/cpu/riscv64/assembler_riscv64.hpp → src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -24,11 +24,11 @@
  *
  */
 
-#ifndef CPU_RISCV64_ASSEMBLER_RISCV64_HPP
-#define CPU_RISCV64_ASSEMBLER_RISCV64_HPP
+#ifndef CPU_RISCV_ASSEMBLER_RISCV_HPP
+#define CPU_RISCV_ASSEMBLER_RISCV_HPP
 
 #include "asm/register.hpp"
-#include "assembler_riscv64.inline.hpp"
+#include "assembler_riscv.inline.hpp"
 
 #define registerSize 64
 
@@ -2243,4 +2243,4 @@ enum Nf {
 
 class BiasedLockingCounters;
 
-#endif // CPU_RISCV64_ASSEMBLER_RISCV64_HPP
+#endif // CPU_RISCV_ASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv64/assembler_riscv64.inline.hpp → src/hotspot/cpu/riscv/assembler_riscv.inline.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_ASSEMBLER_RISCV64_INLINE_HPP
-#define CPU_RISCV64_ASSEMBLER_RISCV64_INLINE_HPP
+#ifndef CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP
+#define CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP
 
 #include "asm/assembler.inline.hpp"
 #include "asm/codeBuffer.hpp"
@@ -44,4 +44,4 @@ inline bool is_offset_in_range(intx offset, unsigned bits) {
   return is_imm_in_range(offset, bits, 0);
 }
 
-#endif // CPU_RISCV64_ASSEMBLER_RISCV64_INLINE_HPP
+#endif // CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP

src/hotspot/cpu/riscv64/bytes_riscv64.hpp → src/hotspot/cpu/riscv/bytes_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_BYTES_RISCV64_HPP
-#define CPU_RISCV64_BYTES_RISCV64_HPP
+#ifndef CPU_RISCV_BYTES_RISCV_HPP
+#define CPU_RISCV_BYTES_RISCV_HPP
 
 #include "memory/allocation.hpp"
 
@@ -164,4 +164,4 @@ class Bytes: AllStatic {
 
 #include OS_CPU_HEADER(bytes)
 
-#endif // CPU_RISCV64_BYTES_RISCV64_HPP
+#endif // CPU_RISCV_BYTES_RISCV_HPP

src/hotspot/cpu/riscv64/c1_CodeStubs_riscv64.cpp → src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp

@@ -32,9 +32,9 @@
 #include "c1/c1_MacroAssembler.hpp"
 #include "c1/c1_Runtime1.hpp"
 #include "classfile/javaClasses.hpp"
-#include "nativeInst_riscv64.hpp"
+#include "nativeInst_riscv.hpp"
 #include "runtime/sharedRuntime.hpp"
-#include "vmreg_riscv64.inline.hpp"
+#include "vmreg_riscv.inline.hpp"
 
 
 #define __ ce->masm()->

src/hotspot/cpu/riscv64/c1_Defs_riscv64.hpp → src/hotspot/cpu/riscv/c1_Defs_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_DEFS_RISCV64_HPP
-#define CPU_RISCV64_C1_DEFS_RISCV64_HPP
+#ifndef CPU_RISCV_C1_DEFS_RISCV_HPP
+#define CPU_RISCV_C1_DEFS_RISCV_HPP
 
 // native word offsets from memory address (little endian)
 enum {
@@ -82,4 +82,4 @@ enum {
   pd_float_saved_as_double = false
 };
 
-#endif // CPU_RISCV64_C1_DEFS_RISCV64_HPP
+#endif // CPU_RISCV_C1_DEFS_RISCV_HPP

src/hotspot/cpu/riscv64/c1_FpuStackSim_riscv64.hpp → src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp

@@ -24,10 +24,10 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_FPUSTACKSIM_HPP
-#define CPU_RISCV64_C1_FPUSTACKSIM_HPP
+#ifndef CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
+#define CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP
 
 // No FPU stack on RISCV64
 class FpuStackSim;
 
-#endif // CPU_RISCV64_C1_FPUSTACKSIM_HPP
+#endif // CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP

src/hotspot/cpu/riscv64/c1_FrameMap_riscv64.cpp → src/hotspot/cpu/riscv/c1_FrameMap_riscv.cpp

@@ -28,7 +28,7 @@
 #include "c1/c1_FrameMap.hpp"
 #include "c1/c1_LIR.hpp"
 #include "runtime/sharedRuntime.hpp"
-#include "vmreg_riscv64.inline.hpp"
+#include "vmreg_riscv.inline.hpp"
 
 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool)
 {

src/hotspot/cpu/riscv64/c1_FrameMap_riscv64.hpp → src/hotspot/cpu/riscv/c1_FrameMap_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_FRAMEMAP_RISCV64_HPP
-#define CPU_RISCV64_C1_FRAMEMAP_RISCV64_HPP
+#ifndef CPU_RISCV_C1_FRAMEMAP_RISCV_HPP
+#define CPU_RISCV_C1_FRAMEMAP_RISCV_HPP
 
 //  On RISCV64 the frame looks as follows:
 //
@@ -146,5 +146,4 @@
   static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; }
   static int last_cpu_reg()             { return pd_last_cpu_reg; }
 
-#endif // CPU_RISCV64_C1_FRAMEMAP_RISCV64_HPP
-
+#endif // CPU_RISCV_C1_FRAMEMAP_RISCV_HPP

src/hotspot/cpu/riscv64/c1_LIRAssembler_arith_riscv64.hpp → src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.hpp

@@ -23,8 +23,8 @@
  * questions.
  *
  */
-#ifndef CPU_RISCV64_C1_LIRASSEMBLER_ARITH_RISCV64_HPP
-#define CPU_RISCV64_C1_LIRASSEMBLER_ARITH_RISCV64_HPP
+#ifndef CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP
+#define CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP
 
   // arith_op sub functions
   void arith_op_single_cpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
@@ -33,4 +33,4 @@
   void arith_op_double_fpu(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest);
   void arith_op_single_cpu_right_constant(LIR_Code code, LIR_Opr left, LIR_Opr right, Register lreg, Register dreg);
   void arithmetic_idiv(LIR_Op3* op, bool is_irem);
-#endif // CPU_RISCV64_C1_LIRASSEMBLER_ARITH_RISCV64_HPP
+#endif // CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP

src/hotspot/cpu/riscv64/c1_LIRAssembler_arraycopy_riscv64.hpp → src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_LIRASSEMBLER_ARRAYCOPY_RISCV64_HPP
-#define CPU_RISCV64_C1_LIRASSEMBLER_ARRAYCOPY_RISCV64_HPP
+#ifndef CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP
+#define CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP
   // arraycopy sub functions
   void generic_arraycopy(Register src, Register src_pos, Register length,
                          Register dst, Register dst_pos, CodeStub *stub);
@@ -48,4 +48,4 @@
                             Register dst, Register dst_pos);
   void arraycopy_load_args(Register src, Register src_pos, Register length,
                            Register dst, Register dst_pos);
-#endif // CPU_RISCV64_C1_LIRASSEMBLER_ARRAYCOPY_RISCV64_HPP
+#endif // CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP

src/hotspot/cpu/riscv64/c1_LIRAssembler_riscv64.cpp → src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

@@ -37,12 +37,12 @@
 #include "ci/ciInstance.hpp"
 #include "code/compiledIC.hpp"
 #include "gc/shared/collectedHeap.hpp"
-#include "nativeInst_riscv64.hpp"
+#include "nativeInst_riscv.hpp"
 #include "oops/objArrayKlass.hpp"
 #include "runtime/frame.inline.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "utilities/powerOfTwo.hpp"
-#include "vmreg_riscv64.inline.hpp"
+#include "vmreg_riscv.inline.hpp"
 
 #ifndef PRODUCT
 #define COMMENT(x)   do { __ block_comment(x); } while (0)

src/hotspot/cpu/riscv64/c1_LIRAssembler_riscv64.hpp → src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp

@@ -24,16 +24,16 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_LIRASSEMBLER_RISCV64_HPP
-#define CPU_RISCV64_C1_LIRASSEMBLER_RISCV64_HPP
+#ifndef CPU_RISCV_C1_LIRASSEMBLER_RISCV_HPP
+#define CPU_RISCV_C1_LIRASSEMBLER_RISCV_HPP
 
 // ArrayCopyStub needs access to bailout
 friend class ArrayCopyStub;
 
 private:
 
-#include "c1_LIRAssembler_arith_riscv64.hpp"
-#include "c1_LIRAssembler_arraycopy_riscv64.hpp"
+#include "c1_LIRAssembler_arith_riscv.hpp"
+#include "c1_LIRAssembler_arraycopy_riscv.hpp"
 
   int array_element_size(BasicType type) const;
 
@@ -128,4 +128,4 @@ friend class ArrayCopyStub;
   void store_parameter(Register r, int offset_from_rsp_in_words);
   void store_parameter(jint c, int offset_from_rsp_in_words);
 
-#endif // CPU_RISCV64_C1_LIRASSEMBLER_RISCV64_HPP
+#endif // CPU_RISCV_C1_LIRASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv64/c1_LIRGenerator_riscv64.cpp → src/hotspot/cpu/riscv/c1_LIRGenerator_riscv.cpp

@@ -39,7 +39,7 @@
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "utilities/powerOfTwo.hpp"
-#include "vmreg_riscv64.inline.hpp"
+#include "vmreg_riscv.inline.hpp"
 
 #ifdef ASSERT
 #define __ gen()->lir(__FILE__, __LINE__)->

src/hotspot/cpu/riscv64/c1_LinearScan_riscv64.hpp → src/hotspot/cpu/riscv/c1_LinearScan_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_LINEARSCAN_RISCV64_HPP
-#define CPU_RISCV64_C1_LINEARSCAN_RISCV64_HPP
+#ifndef CPU_RISCV_C1_LINEARSCAN_RISCV_HPP
+#define CPU_RISCV_C1_LINEARSCAN_RISCV_HPP
 
 inline bool LinearScan::is_processed_reg_num(int reg_num)
 {
@@ -82,4 +82,4 @@ inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur)
 }
 
 
-#endif // CPU_RISCV64_C1_LINEARSCAN_RISCV64_HPP
+#endif // CPU_RISCV_C1_LINEARSCAN_RISCV_HPP

src/hotspot/cpu/riscv64/c1_MacroAssembler_riscv64.hpp → src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_MACROASSEMBLER_RISCV64_HPP
-#define CPU_RISCV64_C1_MACROASSEMBLER_RISCV64_HPP
+#ifndef CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP
+#define CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP
 
 using MacroAssembler::build_frame;
 using MacroAssembler::null_check;
@@ -117,4 +117,4 @@ using MacroAssembler::null_check;
   void c1_float_cmp_branch(int cmpFlag, FloatRegister op1, FloatRegister op2, Label& label,
                            bool is_far, bool is_unordered = false);
 
-#endif // CPU_RISCV64_C1_MACROASSEMBLER_RISCV64_HPP
+#endif // CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv64/c1_Runtime1_riscv64.cpp → src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp

@@ -36,18 +36,18 @@
 #include "gc/shared/cardTableBarrierSet.hpp"
 #include "interpreter/interpreter.hpp"
 #include "memory/universe.hpp"
-#include "nativeInst_riscv64.hpp"
+#include "nativeInst_riscv.hpp"
 #include "oops/compiledICHolder.hpp"
 #include "oops/oop.inline.hpp"
 #include "prims/jvmtiExport.hpp"
-#include "register_riscv64.hpp"
+#include "register_riscv.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/signature.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "runtime/vframe.hpp"
 #include "runtime/vframeArray.hpp"
 #include "utilities/powerOfTwo.hpp"
-#include "vmreg_riscv64.inline.hpp"
+#include "vmreg_riscv.inline.hpp"
 
 
 // Implementation of StubAssembler

src/hotspot/cpu/riscv64/c1_globals_riscv64.hpp → src/hotspot/cpu/riscv/c1_globals_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C1_GLOBALS_RISCV64_HPP
-#define CPU_RISCV64_C1_GLOBALS_RISCV64_HPP
+#ifndef CPU_RISCV_C1_GLOBALS_RISCV_HPP
+#define CPU_RISCV_C1_GLOBALS_RISCV_HPP
 
 #include "utilities/globalDefinitions.hpp"
 #include "utilities/macros.hpp"
@@ -63,4 +63,4 @@ define_pd_global(bool, OptimizeSinglePrecision,      true );
 define_pd_global(bool, CSEArrayLength,               false);
 define_pd_global(bool, TwoOperandLIRForm,            false );
 
-#endif // CPU_RISCV64_C1_GLOBALS_RISCV64_HPP
+#endif // CPU_RISCV_C1_GLOBALS_RISCV_HPP

src/hotspot/cpu/riscv64/c2_MacroAssembler_riscv64.hpp → src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp

@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C2_MACROASSEMBLER_RISCV64_HPP
-#define CPU_RISCV64_C2_MACROASSEMBLER_RISCV64_HPP
+#ifndef CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP
+#define CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP
 
 // C2_MacroAssembler contains high-level macros for C2
 
@@ -181,4 +181,4 @@
                          bool is_double, bool is_min);
 
 
-#endif // CPU_RISCV64_C2_MACROASSEMBLER_RISCV64_HPP
+#endif // CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP

src/hotspot/cpu/riscv64/c2_globals_riscv64.hpp → src/hotspot/cpu/riscv/c2_globals_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_C2_GLOBALS_RISCV64_HPP
-#define CPU_RISCV64_C2_GLOBALS_RISCV64_HPP
+#ifndef CPU_RISCV_C2_GLOBALS_RISCV_HPP
+#define CPU_RISCV_C2_GLOBALS_RISCV_HPP
 
 #include "utilities/globalDefinitions.hpp"
 #include "utilities/macros.hpp"
@@ -81,4 +81,4 @@ define_pd_global(bool, NeverActAsServerClassMachine, false);
 
 define_pd_global(bool,  TrapBasedRangeChecks,        false); // Not needed.
 
-#endif // CPU_RISCV64_C2_GLOBALS_RISCV64_HPP
+#endif // CPU_RISCV_C2_GLOBALS_RISCV_HPP

src/hotspot/cpu/riscv64/codeBuffer_riscv64.hpp → src/hotspot/cpu/riscv/codeBuffer_riscv.hpp

@@ -24,13 +24,13 @@
  *
  */
 
-#ifndef CPU_RISCV64_CODEBUFFER_RISCV64_HPP
-#define CPU_RISCV64_CODEBUFFER_RISCV64_HPP
+#ifndef CPU_RISCV_CODEBUFFER_RISCV_HPP
+#define CPU_RISCV_CODEBUFFER_RISCV_HPP
 
 private:
   void pd_initialize() {}
 
 public:
   void flush_bundle(bool start_new_bundle) {}
 
-#endif // CPU_RISCV64_CODEBUFFER_RISCV64_HPP
+#endif // CPU_RISCV_CODEBUFFER_RISCV_HPP

src/hotspot/cpu/riscv64/copy_riscv64.hpp → src/hotspot/cpu/riscv/copy_riscv.hpp

@@ -24,8 +24,8 @@
  *
  */
 
-#ifndef CPU_RISCV64_COPY_RISCV64_HPP
-#define CPU_RISCV64_COPY_RISCV64_HPP
+#ifndef CPU_RISCV_COPY_RISCV_HPP
+#define CPU_RISCV_COPY_RISCV_HPP
 
 #include OS_CPU_HEADER(copy)
 
@@ -53,4 +53,4 @@ static void pd_zero_to_bytes(void* to, size_t count) {
   (void)memset(to, 0, count);
 }
 
-#endif // CPU_RISCV64_COPY_RISCV64_HPP
+#endif // CPU_RISCV_COPY_RISCV_HPP