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zifeihanRealFYang
zifeihan
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RealFYang
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8295261: RISC-V: Support ReductionV instructions for Vector API
Reviewed-by: yadongwang, dzhang, fyang, eliu
1 parent 556377a commit 087cedc

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4 files changed

+137
-3
lines changed

4 files changed

+137
-3
lines changed

‎src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

+28
Original file line numberDiff line numberDiff line change
@@ -1689,3 +1689,31 @@ bool C2_MacroAssembler::in_scratch_emit_size() {
16891689
}
16901690
return MacroAssembler::in_scratch_emit_size();
16911691
}
1692+
1693+
void C2_MacroAssembler::reduce_operation(Register dst, VectorRegister tmp,
1694+
Register src1, VectorRegister src2,
1695+
BasicType bt, REDUCTION_OP op) {
1696+
Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
1697+
vsetvli(t0, x0, sew);
1698+
1699+
vmv_s_x(tmp, src1);
1700+
1701+
switch (op) {
1702+
case REDUCTION_OP::ADD:
1703+
vredsum_vs(tmp, src2, tmp);
1704+
break;
1705+
case REDUCTION_OP::AND:
1706+
vredand_vs(tmp, src2, tmp);
1707+
break;
1708+
case REDUCTION_OP::OR:
1709+
vredor_vs(tmp, src2, tmp);
1710+
break;
1711+
case REDUCTION_OP::XOR:
1712+
vredxor_vs(tmp, src2, tmp);
1713+
break;
1714+
default:
1715+
ShouldNotReachHere();
1716+
}
1717+
1718+
vmv_x_s(dst, tmp);
1719+
}

‎src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp

+4
Original file line numberDiff line numberDiff line change
@@ -195,4 +195,8 @@
195195
VectorRegister tmp1, VectorRegister tmp2,
196196
bool is_double, bool is_min);
197197

198+
void reduce_operation(Register dst, VectorRegister tmp,
199+
Register src1, VectorRegister src2,
200+
BasicType bt, REDUCTION_OP op);
201+
198202
#endif // CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP

‎src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

+3
Original file line numberDiff line numberDiff line change
@@ -1300,4 +1300,7 @@ class SkipIfEqual {
13001300
~SkipIfEqual();
13011301
};
13021302

1303+
// reduction related operations
1304+
enum REDUCTION_OP {ADD, AND, OR, XOR};
1305+
13031306
#endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP

‎src/hotspot/cpu/riscv/riscv_v.ad

+102-3
Original file line numberDiff line numberDiff line change
@@ -63,9 +63,6 @@ source %{
6363
case Op_ExtractS:
6464
case Op_ExtractUB:
6565
// Vector API specific
66-
case Op_AndReductionV:
67-
case Op_OrReductionV:
68-
case Op_XorReductionV:
6966
case Op_LoadVectorGather:
7067
case Op_StoreVectorScatter:
7168
case Op_VectorBlend:
@@ -809,6 +806,108 @@ instruct vnegD(vReg dst, vReg src) %{
809806
ins_pipe(pipe_slow);
810807
%}
811808

809+
// vector and reduction
810+
811+
instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
812+
predicate(Matcher::vector_element_basic_type(n->in(2)) != T_LONG);
813+
match(Set dst (AndReductionV src1 src2));
814+
effect(TEMP tmp);
815+
ins_cost(VEC_COST);
816+
format %{ "vmv.s.x $tmp, $src1\t#@reduce_andI\n\t"
817+
"vredand.vs $tmp, $src2, $tmp\n\t"
818+
"vmv.x.s $dst, $tmp" %}
819+
ins_encode %{
820+
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
821+
__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
822+
$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::AND);
823+
%}
824+
ins_pipe(pipe_slow);
825+
%}
826+
827+
instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
828+
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
829+
match(Set dst (AndReductionV src1 src2));
830+
effect(TEMP tmp);
831+
ins_cost(VEC_COST);
832+
format %{ "vmv.s.x $tmp, $src1\t#@reduce_andL\n\t"
833+
"vredand.vs $tmp, $src2, $tmp\n\t"
834+
"vmv.x.s $dst, $tmp" %}
835+
ins_encode %{
836+
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
837+
__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
838+
$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::AND);
839+
%}
840+
ins_pipe(pipe_slow);
841+
%}
842+
843+
// vector or reduction
844+
845+
instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
846+
predicate(Matcher::vector_element_basic_type(n->in(2)) != T_LONG);
847+
match(Set dst (OrReductionV src1 src2));
848+
effect(TEMP tmp);
849+
ins_cost(VEC_COST);
850+
format %{ "vmv.s.x $tmp, $src1\t#@reduce_orI\n\t"
851+
"vredor.vs $tmp, $src2, $tmp\n\t"
852+
"vmv.x.s $dst, $tmp" %}
853+
ins_encode %{
854+
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
855+
__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
856+
$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::OR);
857+
%}
858+
ins_pipe(pipe_slow);
859+
%}
860+
861+
instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
862+
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
863+
match(Set dst (OrReductionV src1 src2));
864+
effect(TEMP tmp);
865+
ins_cost(VEC_COST);
866+
format %{ "vmv.s.x $tmp, $src1\t#@reduce_orL\n\t"
867+
"vredor.vs $tmp, $src2, $tmp\n\t"
868+
"vmv.x.s $dst, $tmp" %}
869+
ins_encode %{
870+
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
871+
__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
872+
$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::OR);
873+
%}
874+
ins_pipe(pipe_slow);
875+
%}
876+
877+
// vector xor reduction
878+
879+
instruct reduce_xorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
880+
predicate(Matcher::vector_element_basic_type(n->in(2)) != T_LONG);
881+
match(Set dst (XorReductionV src1 src2));
882+
effect(TEMP tmp);
883+
ins_cost(VEC_COST);
884+
format %{ "vmv.s.x $tmp, $src1\t#@reduce_xorI\n\t"
885+
"vredxor.vs $tmp, $src2, $tmp\n\t"
886+
"vmv.x.s $dst, $tmp" %}
887+
ins_encode %{
888+
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
889+
__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
890+
$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::XOR);
891+
%}
892+
ins_pipe(pipe_slow);
893+
%}
894+
895+
instruct reduce_xorL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
896+
predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
897+
match(Set dst (XorReductionV src1 src2));
898+
effect(TEMP tmp);
899+
ins_cost(VEC_COST);
900+
format %{ "vmv.s.x $tmp, $src1\t#@reduce_xorL\n\t"
901+
"vredxor.vs $tmp, $src2, $tmp\n\t"
902+
"vmv.x.s $dst, $tmp" %}
903+
ins_encode %{
904+
BasicType bt = Matcher::vector_element_basic_type(this, $src2);
905+
__ reduce_operation($dst$$Register, as_VectorRegister($tmp$$reg),
906+
$src1$$Register, as_VectorRegister($src2$$reg), bt, REDUCTION_OP::XOR);
907+
%}
908+
ins_pipe(pipe_slow);
909+
%}
910+
812911
// vector add reduction
813912

814913
instruct reduce_addB(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{

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