Merge branch 'master' of https://github.com/openjdk/jdk into rv32-zero

make/autoconf/util.m4

@@ -239,12 +239,17 @@ AC_DEFUN([UTIL_GET_EPOCH_TIMESTAMP],
     timestamp=$($DATE --utc --date=$2 +"%s" 2> /dev/null)
   else
     # BSD date
-    timestamp=$($DATE -u -j -f "%FZ %TZ" "$2" "+%s" 2> /dev/null)
+    # ISO-8601 date&time in Zulu 'date'T'time'Z
+    timestamp=$($DATE -u -j -f "%FT%TZ" "$2" "+%s" 2> /dev/null)
     if test "x$timestamp" = x; then
       # BSD date cannot handle trailing milliseconds.
       # Try again ignoring characters at end
       timestamp=$($DATE -u -j -f "%Y-%m-%dT%H:%M:%S" "$2" "+%s" 2> /dev/null)
     fi
+    if test "x$timestamp" = x; then
+      # Perhaps the time was missing.
+      timestamp=$($DATE -u -j -f "%FT%TZ" "$2""T00:00:00Z" "+%s" 2> /dev/null)
+    fi
   fi
   $1=$timestamp
 ])

make/common/NativeCompilation.gmk

@@ -358,6 +358,20 @@ define SetupCompileNativeFileBody
       # Compile as preprocessed assembler file
       $1_FLAGS := $(BASIC_ASFLAGS) $$($1_BASE_ASFLAGS)
       $1_COMPILER := $(AS)
+
+      # gcc assembly files must contain an appropriate relative .file
+      # path for reproducible builds.
+      ifeq ($(TOOLCHAIN_TYPE), gcc)
+        # If no absolute paths allowed, work out relative source file path
+        # for assembly .file substitution, otherwise use full file path
+        ifeq ($(ALLOW_ABSOLUTE_PATHS_IN_OUTPUT), false)
+          $1_REL_ASM_SRC := $$(call RelativePath, $$($1_FILE), $(WORKSPACE_ROOT))
+        else
+          $1_REL_ASM_SRC := $$($1_FILE)
+        endif
+        $1_FLAGS := $$($1_FLAGS) -DASSEMBLY_SRC_FILE='"$$($1_REL_ASM_SRC)"' \
+            -include $(TOPDIR)/make/data/autoheaders/assemblyprefix.h
+      endif
     else ifneq ($$(filter %.cpp %.cc %.mm, $$($1_FILENAME)), )
       # Compile as a C++ or Objective-C++ file
       $1_FLAGS := $(CFLAGS_CCACHE) $$($1_USE_PCH_FLAGS) $$($1_BASE_CXXFLAGS) \
@@ -1149,19 +1163,6 @@ define SetupNativeCompilationBody
       endif
     endif
 
-    # Debuginfo of ASM objects always embeds the absolute object path,
-    # as ASM debuginfo paths do not get prefix mapped.
-    # So for reproducible builds use relative paths to ensure a reproducible
-    # debuginfo and libs, when creating debug symbols.
-    ifeq ($$(ENABLE_REPRODUCIBLE_BUILD), true)
-      ifeq ($(call isTargetOs, linux), true)
-        ifeq ($$($1_COMPILE_WITH_DEBUG_SYMBOLS), true)
-          $1_LINK_OBJS_RELATIVE := true
-          $1_ALL_OBJS_RELATIVE := $$(patsubst $$(OUTPUTDIR)/%, %, $$($1_ALL_OBJS))
-        endif
-      endif
-    endif
-
     $1_TARGET_DEPS := $$($1_ALL_OBJS) $$($1_RES) $$($1_MANIFEST) \
         $$($1_REAL_MAPFILE) $$($1_VARDEPS_FILE)
 

make/data/autoheaders/assemblyprefix.h

@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
+# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+#
+# This code is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 only, as
+# published by the Free Software Foundation.
+#
+# This code is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# version 2 for more details (a copy is included in the LICENSE file that
+# accompanied this code).
+#
+# You should have received a copy of the GNU General Public License version
+# 2 along with this work; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+# or visit www.oracle.com if you need additional information or have any
+# questions.
+#
+
+// ASSEMBLY_SRC_FILE gets replaced by relative or absolute file path
+// in NativeCompilation.gmk for gcc tooling on Linux. This ensures a
+// reproducible object file through a predictable value of the STT_FILE
+// symbol, and subsequently a reproducible .debuginfo.
+.file ASSEMBLY_SRC_FILE
+

make/test/BuildMicrobenchmark.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -94,7 +94,8 @@ $(eval $(call SetupJavaCompilation, BUILD_JDK_MICROBENCHMARK, \
     DISABLED_WARNINGS := processing rawtypes cast serial, \
     SRC := $(MICROBENCHMARK_SRC), \
     BIN := $(MICROBENCHMARK_CLASSES), \
-    JAVAC_FLAGS := --add-exports java.base/sun.security.util=ALL-UNNAMED, \
+    JAVAC_FLAGS := --add-exports java.base/sun.security.util=ALL-UNNAMED \
+        --add-exports java.base/sun.invoke.util=ALL-UNNAMED, \
     JAVA_FLAGS := --add-modules jdk.unsupported --limit-modules java.management, \
 ))
 

src/hotspot/cpu/aarch64/aarch64.ad

@@ -28,7 +28,7 @@
 //----------REGISTER DEFINITION BLOCK------------------------------------------
 // This information is used by the matcher and the register allocator to
 // describe individual registers and classes of registers within the target
-// archtecture.
+// architecture.
 
 register %{
 //----------Architecture Description Register Definitions----------------------
@@ -488,7 +488,7 @@ reg_def R31_H   (  NS,  NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
 // Special Registers
 // ----------------------------
 
-// the AArch64 CSPR status flag register is not directly acessible as
+// the AArch64 CSPR status flag register is not directly accessible as
 // instruction operand. the FPSR status flag register is a system
 // register which can be written/read using MSR/MRS but again does not
 // appear as an operand (a code identifying the FSPR occurs as an
@@ -1508,7 +1508,7 @@ source %{
   // node sequence to a normal volatile get because of the
   // introduction of some CPUOrder memory barriers to bracket the
   // Load. However, but the same basic skeleton of a LoadX feeding a
-  // MemBarAcquire, possibly thorugh an optional DecodeN, is still
+  // MemBarAcquire, possibly through an optional DecodeN, is still
   // present
   //
   //   MemBarCPUOrder
@@ -4117,10 +4117,10 @@ encode %{
 //         Region 6-7 is determined per call site.
 // Note 2: If the calling convention leaves holes in the incoming argument
 //         area, those holes are owned by SELF.  Holes in the outgoing area
-//         are owned by the CALLEE.  Holes should not be nessecary in the
+//         are owned by the CALLEE.  Holes should not be necessary in the
 //         incoming area, as the Java calling convention is completely under
 //         the control of the AD file.  Doubles can be sorted and packed to
-//         avoid holes.  Holes in the outgoing arguments may be nessecary for
+//         avoid holes.  Holes in the outgoing arguments may be necessary for
 //         varargs C calling conventions.
 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 //         even aligned with pad0 as needed.
@@ -17344,7 +17344,7 @@ instruct tlsLoadP(thread_RegP dst)
 //
 // // Change (inc mov) to lea
 // peephole %{
-//   // increment preceeded by register-register move
+//   // increment preceded by register-register move
 //   peepmatch ( incI_iReg movI );
 //   // require that the destination register of the increment
 //   // match the destination register of the move

src/hotspot/cpu/aarch64/aarch64_neon.ad

@@ -5844,7 +5844,7 @@ instruct vmask_lasttrue8B(iRegINoSp dst, vecD src) %{
     // bytes with 0x00/0x01 as element values.
     //
     // Computed by counting the leading zero bytes and
-    // substracting it by 7 (VLENGTH - 1).
+    // subtracting it by 7 (VLENGTH - 1).
     __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
     __ clz($dst$$Register, $dst$$Register);
     __ movw(rscratch1, 7);
@@ -5876,7 +5876,7 @@ instruct vmask_lasttrue16B(iRegINoSp dst, vecX src) %{
     __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
     __ movw(rscratch1, 8 - 1);
 
-    // Count the leading zero bytes and substract it by 15 (VLENGTH - 1).
+    // Count the leading zero bytes and subtract it by 15 (VLENGTH - 1).
     __ bind(LAST_TRUE_INDEX);
     __ clz($dst$$Register, $dst$$Register);
     __ subw($dst$$Register, rscratch1, $dst$$Register, Assembler::LSR, 3);

src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

@@ -2548,7 +2548,7 @@ instruct vmask_lasttrue8B(iRegINoSp dst, vecD src) %{
     // bytes with 0x00/0x01 as element values.
     //
     // Computed by counting the leading zero bytes and
-    // substracting it by 7 (VLENGTH - 1).
+    // subtracting it by 7 (VLENGTH - 1).
     __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
     __ clz($dst$$Register, $dst$$Register);
     __ movw(rscratch1, 7);
@@ -2580,7 +2580,7 @@ instruct vmask_lasttrue16B(iRegINoSp dst, vecX src) %{
     __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
     __ movw(rscratch1, 8 - 1);
 
-    // Count the leading zero bytes and substract it by 15 (VLENGTH - 1).
+    // Count the leading zero bytes and subtract it by 15 (VLENGTH - 1).
     __ bind(LAST_TRUE_INDEX);
     __ clz($dst$$Register, $dst$$Register);
     __ subw($dst$$Register, rscratch1, $dst$$Register, Assembler::LSR, 3);

src/hotspot/cpu/aarch64/abstractInterpreter_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -86,7 +86,7 @@ int AbstractInterpreter::size_activation(int max_stack,
   int overhead = frame::sender_sp_offset -
                  frame::interpreter_frame_initial_sp_offset;
   // Our locals were accounted for by the caller (or last_frame_adjust
-  // on the transistion) Since the callee parameters already account
+  // on the transition) Since the callee parameters already account
   // for the callee's params we only need to account for the extra
   // locals.
   int size = overhead +

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -36,7 +36,7 @@
 
 #elif defined(_MSC_VER)
 
-// Use MSVC instrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
+// Use MSVC intrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
 #define NOP() __nop();
 
 #endif
@@ -593,7 +593,7 @@ class Address {
   }
 };
 
-// Convience classes
+// Convenience classes
 class RuntimeAddress: public Address {
 
   public:

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

@@ -433,7 +433,7 @@ int LIR_Assembler::emit_unwind_handler() {
     __ mov(r19, r0);  // Preserve the exception
   }
 
-  // Preform needed unlocking
+  // Perform needed unlocking
   MonitorExitStub* stub = NULL;
   if (method()->is_synchronized()) {
     monitor_address(0, FrameMap::r0_opr);

src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp

@@ -692,7 +692,7 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
           }
 #endif // ASSERT
 
-          // get the instance size (size is postive so movl is fine for 64bit)
+          // get the instance size (size is positive so movl is fine for 64bit)
           __ ldrw(obj_size, Address(klass, Klass::layout_helper_offset()));
 
           __ eden_allocate(obj, obj_size, 0, t1, slow_path);

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -80,7 +80,7 @@ void C2_MacroAssembler::string_indexof(Register str2, Register str1,
   // if (substr.count == 0) return 0;
 
   // We have two strings, a source string in str2, cnt2 and a pattern string
-  // in str1, cnt1. Find the 1st occurence of pattern in source or return -1.
+  // in str1, cnt1. Find the 1st occurrence of pattern in source or return -1.
 
   // For larger pattern and source we use a simplified Boyer Moore algorithm.
   // With a small pattern and source we use linear scan.

src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp

@@ -186,7 +186,7 @@ void ShenandoahBarrierSetAssembler::resolve_forward_pointer(MacroAssembler* masm
   __ bind(is_null);
 }
 
-// IMPORTANT: This must preserve all registers, even rscratch1 and rscratch2, except those explicitely
+// IMPORTANT: This must preserve all registers, even rscratch1 and rscratch2, except those explicitly
 // passed in.
 void ShenandoahBarrierSetAssembler::resolve_forward_pointer_not_null(MacroAssembler* masm, Register dst, Register tmp) {
   assert(ShenandoahLoadRefBarrier || ShenandoahCASBarrier, "Should be enabled");

src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp

@@ -237,7 +237,7 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_stub(LIR_Assembler* ce,
   assert_different_registers(ref, ref_addr, noreg);
 
   // Save r0 unless it is the result or tmp register
-  // Set up SP to accomodate parameters and maybe r0..
+  // Set up SP to accommodate parameters and maybe r0..
   if (ref != r0 && tmp != r0) {
     __ sub(sp, sp, 32);
     __ str(r0, Address(sp, 16));

src/hotspot/cpu/aarch64/gc/z/zGlobals_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2017, 2022, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -154,12 +154,12 @@ static size_t probe_valid_max_address_bit() {
   for (size_t i = DEFAULT_MAX_ADDRESS_BIT; i > MINIMUM_MAX_ADDRESS_BIT; --i) {
     const uintptr_t base_addr = ((uintptr_t) 1U) << i;
     if (msync((void*)base_addr, page_size, MS_ASYNC) == 0) {
-      // msync suceeded, the address is valid, and maybe even already mapped.
+      // msync succeeded, the address is valid, and maybe even already mapped.
       max_address_bit = i;
       break;
     }
     if (errno != ENOMEM) {
-      // Some error occured. This should never happen, but msync
+      // Some error occurred. This should never happen, but msync
       // has some undefined behavior, hence ignore this bit.
 #ifdef ASSERT
       fatal("Received '%s' while probing the address space for the highest valid bit", os::errno_name(errno));

src/hotspot/cpu/aarch64/globals_aarch64.hpp

@@ -91,7 +91,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(bool, UseSIMDForArrayEquals, true,                            \
           "Use SIMD instructions in generated array equals code")       \
   product(bool, UseSimpleArrayEquals, false,                            \
-          "Use simpliest and shortest implementation for array equals") \
+          "Use simplest and shortest implementation for array equals")  \
   product(bool, UseSIMDForBigIntegerShiftIntrinsics, true,              \
           "Use SIMD instructions for left/right shift of BigInteger")   \
   product(bool, AvoidUnalignedAccesses, false,                          \

src/hotspot/cpu/aarch64/immediate_aarch64.cpp

@@ -257,7 +257,7 @@ int expandLogicalImmediate(uint32_t immN, uint32_t immr,
 // constructor to initialise the lookup tables
 
 static void initLITables();
-// Use an empty struct with a construtor as MSVC doesn't support `__attribute__ ((constructor))`
+// Use an empty struct with a constructor as MSVC doesn't support `__attribute__ ((constructor))`
 // See https://stackoverflow.com/questions/1113409/attribute-constructor-equivalent-in-vc
 static struct initLITables_t { initLITables_t(void) { initLITables(); } } _initLITables;
 static void initLITables()

src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -523,7 +523,7 @@ void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {
 //
 // Apply stack watermark barrier.
 // Unlock the receiver if this is a synchronized method.
-// Unlock any Java monitors from syncronized blocks.
+// Unlock any Java monitors from synchronized blocks.
 // Remove the activation from the stack.
 //
 // If there are locked Java monitors
@@ -1748,7 +1748,7 @@ void InterpreterMacroAssembler::profile_return_type(Register mdp, Register ret,
 
       // If we don't profile all invoke bytecodes we must make sure
       // it's a bytecode we indeed profile. We can't go back to the
-      // begining of the ProfileData we intend to update to check its
+      // beginning of the ProfileData we intend to update to check its
       // type because we're right after it and we don't known its
       // length
       Label do_profile;

src/hotspot/cpu/aarch64/interp_masm_aarch64.hpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -30,7 +30,7 @@
 #include "interpreter/invocationCounter.hpp"
 #include "runtime/frame.hpp"
 
-// This file specializes the assember with interpreter-specific macros
+// This file specializes the assembler with interpreter-specific macros
 
 typedef ByteSize (*OffsetFunction)(uint);