Merge branch 'openjdk:master' into patch-6

make/Images.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014, 2020, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -114,67 +114,55 @@ $(eval $(call SetupExecute, jlink_jre, \
 
 JLINK_JRE_TARGETS := $(jlink_jre)
 
-ifeq ($(BUILD_CDS_ARCHIVE), true)
+# Helper function for creating the CDS archives for the JDK and JRE
+#
+# Param1 - VM variant (e.g., server, client, zero, ...)
+# Param2 - _nocoops, or empty
+define CreateCDSArchive
+  $1_$2_DUMP_EXTRA_ARG := $(if $(filter _nocoops, $2),-XX:-UseCompressedOops,)
+  $1_$2_DUMP_TYPE      := $(if $(filter _nocoops, $2),-NOCOOPS,)
+
   ifeq ($(OPENJDK_TARGET_OS), windows)
-    CDS_ARCHIVE := bin/server/classes.jsa
-    CDS_NOCOOPS_ARCHIVE := bin/server/classes_nocoops.jsa
+    $1_$2_CDS_ARCHIVE := bin/$1/classes$2.jsa
   else
-    CDS_ARCHIVE := lib/server/classes.jsa
-    CDS_NOCOOPS_ARCHIVE := lib/server/classes_nocoops.jsa
+    $1_$2_CDS_ARCHIVE := lib/$1/classes$2.jsa
   endif
 
-  $(eval $(call SetupExecute, gen_cds_archive_jdk, \
-      WARN := Creating CDS archive for jdk image, \
-      DEPS := $(jlink_jdk), \
-      OUTPUT_FILE := $(JDK_IMAGE_DIR)/$(CDS_ARCHIVE), \
-      SUPPORT_DIR := $(SUPPORT_OUTPUTDIR)/images/jdk, \
-      COMMAND := $(FIXPATH) $(JDK_IMAGE_DIR)/bin/java -Xshare:dump \
-          -XX:SharedArchiveFile=$(JDK_IMAGE_DIR)/$(CDS_ARCHIVE) \
-          -Xmx128M -Xms128M $(LOG_INFO), \
+  $$(eval $$(call SetupExecute, $1_$2_gen_cds_archive_jdk, \
+      WARN := Creating CDS$$($1_$2_DUMP_TYPE) archive for jdk image for $1, \
+      DEPS := $$(jlink_jdk), \
+      OUTPUT_FILE := $$(JDK_IMAGE_DIR)/$$($1_$2_CDS_ARCHIVE), \
+      SUPPORT_DIR := $$(SUPPORT_OUTPUTDIR)/images/jdk, \
+      COMMAND := $$(FIXPATH) $$(JDK_IMAGE_DIR)/bin/java -Xshare:dump \
+          -XX:SharedArchiveFile=$$(JDK_IMAGE_DIR)/$$($1_$2_CDS_ARCHIVE) \
+          -$1 $$($1_$2_DUMP_EXTRA_ARG) -Xmx128M -Xms128M $$(LOG_INFO), \
   ))
 
-  JDK_TARGETS += $(gen_cds_archive_jdk)
+  JDK_TARGETS += $$($1_$2_gen_cds_archive_jdk)
 
-  $(eval $(call SetupExecute, gen_cds_archive_jre, \
-      WARN := Creating CDS archive for jre image, \
-      DEPS := $(jlink_jre), \
-      OUTPUT_FILE := $(JRE_IMAGE_DIR)/$(CDS_ARCHIVE), \
-      SUPPORT_DIR := $(SUPPORT_OUTPUTDIR)/images/jre, \
-      COMMAND := $(FIXPATH) $(JRE_IMAGE_DIR)/bin/java -Xshare:dump \
-          -XX:SharedArchiveFile=$(JRE_IMAGE_DIR)/$(CDS_ARCHIVE) \
-          -Xmx128M -Xms128M $(LOG_INFO), \
+  $$(eval $$(call SetupExecute, $1_$2_gen_cds_archive_jre, \
+      WARN := Creating CDS$$($1_$2_DUMP_TYPE) archive for jre image for $1, \
+      DEPS := $$(jlink_jre), \
+      OUTPUT_FILE := $$(JRE_IMAGE_DIR)/$$($1_$2_CDS_ARCHIVE), \
+      SUPPORT_DIR := $$(SUPPORT_OUTPUTDIR)/images/jre, \
+      COMMAND := $$(FIXPATH) $$(JRE_IMAGE_DIR)/bin/java -Xshare:dump \
+          -XX:SharedArchiveFile=$$(JRE_IMAGE_DIR)/$$($1_$2_CDS_ARCHIVE) \
+          -$1 $$($1_$2_DUMP_EXTRA_ARG) -Xmx128M -Xms128M $$(LOG_INFO), \
   ))
 
-  JRE_TARGETS += $(gen_cds_archive_jre)
+  JRE_TARGETS += $$($1_$2_gen_cds_archive_jre)
+endef
+
+ifeq ($(BUILD_CDS_ARCHIVE), true)
+  $(foreach v, $(JVM_VARIANTS), \
+    $(eval $(call CreateCDSArchive,$v,)) \
+  )
 
   ifeq ($(call isTargetCpuBits, 64), true)
-    $(eval $(call SetupExecute, gen_cds_nocoops_archive_jdk, \
-        WARN := Creating CDS-NOCOOPS archive for jdk image, \
-        DEPS := $(jlink_jdk), \
-        OUTPUT_FILE := $(JDK_IMAGE_DIR)/$(CDS_NOCOOPS_ARCHIVE), \
-        SUPPORT_DIR := $(SUPPORT_OUTPUTDIR)/images/jdk, \
-        COMMAND := $(FIXPATH) $(JDK_IMAGE_DIR)/bin/java -Xshare:dump \
-            -XX:SharedArchiveFile=$(JDK_IMAGE_DIR)/$(CDS_NOCOOPS_ARCHIVE) \
-            -XX:-UseCompressedOops \
-            -Xmx128M -Xms128M $(LOG_INFO), \
-    ))
-
-    JDK_TARGETS += $(gen_cds_nocoops_archive_jdk)
-
-    $(eval $(call SetupExecute, gen_cds_nocoops_archive_jre, \
-        WARN := Creating CDS-NOCOOPS archive for jre image, \
-        DEPS := $(jlink_jre), \
-        OUTPUT_FILE := $(JRE_IMAGE_DIR)/$(CDS_NOCOOPS_ARCHIVE), \
-        SUPPORT_DIR := $(SUPPORT_OUTPUTDIR)/images/jre, \
-        COMMAND := $(FIXPATH) $(JRE_IMAGE_DIR)/bin/java -Xshare:dump \
-            -XX:SharedArchiveFile=$(JRE_IMAGE_DIR)/$(CDS_NOCOOPS_ARCHIVE) \
-            -XX:-UseCompressedOops \
-            -Xmx128M -Xms128M $(LOG_INFO), \
-    ))
-
-    JRE_TARGETS += $(gen_cds_nocoops_archive_jre)
+    $(foreach v, $(JVM_VARIANTS), \
+      $(eval $(call CreateCDSArchive,$v,_nocoops)) \
+    )
   endif
-
 endif
 
 ################################################################################

make/autoconf/jvm-features.m4

@@ -410,7 +410,7 @@ AC_DEFUN([JVM_FEATURES_PREPARE_VARIANT],
   elif test "x$variant" = "xcore"; then
     JVM_FEATURES_VARIANT_UNAVAILABLE="cds minimal zero"
   elif test "x$variant" = "xzero"; then
-    JVM_FEATURES_VARIANT_UNAVAILABLE="cds compiler1 compiler2 \
+    JVM_FEATURES_VARIANT_UNAVAILABLE="compiler1 compiler2 \
         jvmci minimal zgc"
   else
     JVM_FEATURES_VARIANT_UNAVAILABLE="minimal zero"

make/common/Utils.gmk

@@ -367,6 +367,9 @@ isBuildCpu = \
 isBuildCpuArch = \
   $(strip $(if $(filter $(OPENJDK_BUILD_CPU_ARCH), $1), true, false))
 
+isCompiler = \
+  $(strip $(if $(filter $(TOOLCHAIN_TYPE), $1), true, false))
+
 ################################################################################
 # Converts a space separated list to a comma separated list.
 #

make/hotspot/lib/JvmFeatures.gmk

@@ -169,12 +169,13 @@ endif
 ################################################################################
 
 ifeq ($(call check-jvm-feature, link-time-opt), true)
-  # NOTE: Disable automatic opimization level and let the explicit cflag control
-  # optimization level instead. This activates O3 on slowdebug builds, just
-  # like the old build, but it's probably not right.
-  JVM_OPTIMIZATION :=
-  JVM_CFLAGS_FEATURES += -O3 -flto
-  JVM_LDFLAGS_FEATURES += -O3 -flto -fuse-linker-plugin -fno-strict-aliasing
+  # Set JVM_OPTIMIZATION directly so other jvm-feature flags can override it
+  # later on if desired
+  JVM_OPTIMIZATION := HIGHEST_JVM
+  ifeq ($(call isCompiler, gcc), true)
+    JVM_CFLAGS_FEATURES += -flto -fuse-linker-plugin
+    JVM_LDFLAGS_FEATURES += -flto -fuse-linker-plugin -fno-strict-aliasing
+  endif
 endif
 
 ifeq ($(call check-jvm-feature, opt-size), true)

make/test/JtregNativeHotspot.gmk

@@ -874,7 +874,7 @@ BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exesigtest := -ljvm
 
 ifeq ($(call isTargetOs, windows), true)
   BUILD_HOTSPOT_JTREG_EXECUTABLES_CFLAGS_exeFPRegs := -MT
-  BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c libTestJNI.c libCompleteExit.c
+  BUILD_HOTSPOT_JTREG_EXCLUDE += exesigtest.c libterminatedThread.c libTestJNI.c libCompleteExit.c libTestPsig.c
   BUILD_HOTSPOT_JTREG_LIBRARIES_LIBS_libatExit := jvm.lib
   BUILD_HOTSPOT_JTREG_EXECUTABLES_LIBS_exedaemonDestroy := jvm.lib
 else

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -6359,3 +6359,36 @@ instruct vexpand(vReg dst, vReg src, pRegGov pg) %{
   %}
   ins_pipe(pipe_slow);
 %}
+
+// ------------------------------ Vector signum --------------------------------
+
+// Vector Math.signum
+
+instruct vsignum_le128b(vReg dst, vReg src, vReg zero, vReg one) %{
+  predicate(Matcher::vector_length_in_bytes(n) <= 16);
+  match(Set dst (SignumVF src (Binary zero one)));
+  match(Set dst (SignumVD src (Binary zero one)));
+  effect(TEMP_DEF dst);
+  format %{ "vsignum_le128b $dst, $src\t# vector <= 128 bits" %}
+  ins_encode %{
+    __ vector_signum_neon($dst$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister,
+                          $one$$FloatRegister, get_arrangement(this));
+  %}
+  ins_pipe(pipe_slow);
+%}
+
+instruct vsignum_gt128b(vReg dst, vReg src, vReg zero, vReg one, vReg tmp, pRegGov pgtmp) %{
+  predicate(Matcher::vector_length_in_bytes(n) > 16);
+  match(Set dst (SignumVF src (Binary zero one)));
+  match(Set dst (SignumVD src (Binary zero one)));
+  effect(TEMP_DEF dst, TEMP tmp, TEMP pgtmp);
+  format %{ "vsignum_gt128b $dst, $src\t# vector > 128 bits. KILL $tmp, $pgtmp" %}
+  ins_encode %{
+    assert(UseSVE > 0, "must be sve");
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    __ vector_signum_sve($dst$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister,
+                         $one$$FloatRegister, $tmp$$FloatRegister, $pgtmp$$PRegister,
+                         __ elemType_to_regVariant(bt));
+  %}
+  ins_pipe(pipe_slow);
+%}

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -4699,3 +4699,36 @@ instruct vexpand(vReg dst, vReg src, pRegGov pg) %{
   %}
   ins_pipe(pipe_slow);
 %}
+
+// ------------------------------ Vector signum --------------------------------
+
+// Vector Math.signum
+
+instruct vsignum_le128b(vReg dst, vReg src, vReg zero, vReg one) %{
+  predicate(Matcher::vector_length_in_bytes(n) <= 16);
+  match(Set dst (SignumVF src (Binary zero one)));
+  match(Set dst (SignumVD src (Binary zero one)));
+  effect(TEMP_DEF dst);
+  format %{ "vsignum_le128b $dst, $src\t# vector <= 128 bits" %}
+  ins_encode %{
+    __ vector_signum_neon($dst$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister,
+                          $one$$FloatRegister, get_arrangement(this));
+  %}
+  ins_pipe(pipe_slow);
+%}
+
+instruct vsignum_gt128b(vReg dst, vReg src, vReg zero, vReg one, vReg tmp, pRegGov pgtmp) %{
+  predicate(Matcher::vector_length_in_bytes(n) > 16);
+  match(Set dst (SignumVF src (Binary zero one)));
+  match(Set dst (SignumVD src (Binary zero one)));
+  effect(TEMP_DEF dst, TEMP tmp, TEMP pgtmp);
+  format %{ "vsignum_gt128b $dst, $src\t# vector > 128 bits. KILL $tmp, $pgtmp" %}
+  ins_encode %{
+    assert(UseSVE > 0, "must be sve");
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    __ vector_signum_sve($dst$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister,
+                         $one$$FloatRegister, $tmp$$FloatRegister, $pgtmp$$PRegister,
+                         __ elemType_to_regVariant(bt));
+  %}
+  ins_pipe(pipe_slow);
+%}

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -2566,6 +2566,7 @@ void mvnw(Register Rd, Register Rm,
   INSN(fcmeq, 0, 0, 0b111001);
   INSN(fcmgt, 1, 1, 0b111001);
   INSN(fcmge, 1, 0, 0b111001);
+  INSN(facgt, 1, 1, 0b111011);
 
 #undef INSN
 
@@ -3512,18 +3513,22 @@ void mvnw(Register Rd, Register Rm,
   void NAME(Condition cond, PRegister Pd, SIMD_RegVariant T, PRegister Pg,             \
             FloatRegister Zn, FloatRegister Zm) {                                      \
     starti;                                                                            \
-    if (fp == 0) {                                                                     \
-      assert(T != Q, "invalid size");                                                  \
-    } else {                                                                           \
-      assert(T != B && T != Q, "invalid size");                                        \
-      assert(cond != HI && cond != HS, "invalid condition for fcm");                   \
+    assert(T != Q, "invalid size");                                                    \
+    bool is_absolute = op2 == 0b11;                                                    \
+    if (fp == 1) {                                                                     \
+      assert(T != B, "invalid size");                                                  \
+      if (is_absolute) {                                                               \
+        assert(cond == GT || cond == GE, "invalid condition for fac");                 \
+      } else {                                                                         \
+        assert(cond != HI && cond != HS, "invalid condition for fcm");                 \
+      }                                                                                \
     }                                                                                  \
     int cond_op;                                                                       \
     switch(cond) {                                                                     \
       case EQ: cond_op = (op2 << 2) | 0b10; break;                                     \
       case NE: cond_op = (op2 << 2) | 0b11; break;                                     \
-      case GE: cond_op = (op2 << 2) | 0b00; break;                                     \
-      case GT: cond_op = (op2 << 2) | 0b01; break;                                     \
+      case GE: cond_op = (op2 << 2) | (is_absolute ? 0b01 : 0b00); break;              \
+      case GT: cond_op = (op2 << 2) | (is_absolute ? 0b11 : 0b01); break;              \
       case HI: cond_op = 0b0001; break;                                                \
       case HS: cond_op = 0b0000; break;                                                \
       default:                                                                         \
@@ -3533,8 +3538,9 @@ void mvnw(Register Rd, Register Rm,
     pgrf(Pg, 10), rf(Zn, 5), f(cond_op & 1, 4), prf(Pd, 0);                            \
   }
 
-  INSN(sve_cmp, 0b00100100, 0b10, 0);
-  INSN(sve_fcm, 0b01100101, 0b01, 1);
+  INSN(sve_cmp, 0b00100100, 0b10, 0); // Integer compare vectors
+  INSN(sve_fcm, 0b01100101, 0b01, 1); // Floating-point compare vectors
+  INSN(sve_fac, 0b01100101, 0b11, 1); // Floating-point absolute compare vectors
 #undef INSN
 
 // SVE Integer Compare - Signed Immediate

src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp

@@ -35,6 +35,7 @@
 #include "ci/ciArray.hpp"
 #include "ci/ciObjArrayKlass.hpp"
 #include "ci/ciTypeArrayKlass.hpp"
+#include "compiler/compilerDefinitions.inline.hpp"
 #include "runtime/sharedRuntime.hpp"
 #include "runtime/stubRoutines.hpp"
 #include "utilities/powerOfTwo.hpp"

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

@@ -2009,6 +2009,41 @@ void C2_MacroAssembler::vector_round_sve(FloatRegister dst, FloatRegister src, F
   // result in dst
 }
 
+void C2_MacroAssembler::vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
+                                           FloatRegister one, SIMD_Arrangement T) {
+  assert_different_registers(dst, src, zero, one);
+  assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
+
+  facgt(dst, T, src, zero);
+  ushr(dst, T, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
+  bsl(dst, T == T2S ? T8B : T16B, one, src); // Result in dst
+}
+
+void C2_MacroAssembler::vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
+                                          FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T) {
+    assert_different_registers(dst, src, zero, one, vtmp);
+    assert(pgtmp->is_governing(), "This register has to be a governing predicate register");
+
+    sve_orr(vtmp, src, src);
+    sve_fac(Assembler::GT, pgtmp, T, ptrue, src, zero); // pmtp=0 for +-0.0 and NaN. 0x1 otherwise
+    switch (T) {
+    case S:
+      sve_and(vtmp, T, min_jint); // Extract the sign bit of float value in every lane of src
+      sve_orr(vtmp, T, jint_cast(1.0)); // OR it with +1 to make the final result +1 or -1 depending
+                                        // on the sign of the float value
+      break;
+    case D:
+      sve_and(vtmp, T, min_jlong);
+      sve_orr(vtmp, T, jlong_cast(1.0));
+      break;
+    default:
+      assert(false, "unsupported");
+      ShouldNotReachHere();
+    }
+    sve_sel(dst, T, pgtmp, vtmp, src); // Select either from src or vtmp based on the predicate register pgtmp
+                                       // Result in dst
+}
+
 bool C2_MacroAssembler::in_scratch_emit_size() {
   if (ciEnv::current()->task() != NULL) {
     PhaseOutput* phase_output = Compile::current()->output();
@@ -2018,4 +2053,3 @@ bool C2_MacroAssembler::in_scratch_emit_size() {
   }
   return MacroAssembler::in_scratch_emit_size();
 }
-

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

@@ -165,4 +165,11 @@
 
   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
 
+  // java.lang.Math::signum intrinsics
+  void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
+                          FloatRegister one, SIMD_Arrangement T);
+
+  void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
+                         FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
+
 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

src/hotspot/cpu/aarch64/frame_aarch64.hpp

@@ -26,8 +26,6 @@
 #ifndef CPU_AARCH64_FRAME_AARCH64_HPP
 #define CPU_AARCH64_FRAME_AARCH64_HPP
 
-#include "runtime/synchronizer.hpp"
-
 // A frame represents a physical stack frame (an activation).  Frames can be
 // C or Java frames, and the Java frames can be interpreted or compiled.
 // In contrast, vframes represent source-level activations, so that one physical frame

src/hotspot/cpu/aarch64/gc/shenandoah/c1/shenandoahBarrierSetC1_aarch64.cpp

@@ -25,6 +25,7 @@
 #include "precompiled.hpp"
 #include "c1/c1_LIRAssembler.hpp"
 #include "c1/c1_MacroAssembler.hpp"
+#include "compiler/compilerDefinitions.inline.hpp"
 #include "gc/shared/gc_globals.hpp"
 #include "gc/shenandoah/shenandoahBarrierSet.hpp"
 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"

src/hotspot/cpu/aarch64/templateTable_aarch64.cpp

@@ -25,6 +25,7 @@
 
 #include "precompiled.hpp"
 #include "asm/macroAssembler.inline.hpp"
+#include "compiler/compilerDefinitions.inline.hpp"
 #include "gc/shared/barrierSetAssembler.hpp"
 #include "gc/shared/collectedHeap.hpp"
 #include "gc/shared/tlab_globals.hpp"

src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

@@ -104,7 +104,7 @@ class VM_Version : public Abstract_VM_Version {
 
 #define CPU_FEATURE_FLAGS(decl)               \
     decl(FP,            fp,            0)     \
-    decl(ASIMD,         simd,          1)     \
+    decl(ASIMD,         asimd,         1)     \
     decl(EVTSTRM,       evtstrm,       2)     \
     decl(AES,           aes,           3)     \
     decl(PMULL,         pmull,         4)     \

src/hotspot/cpu/arm/frame_arm.hpp

@@ -25,8 +25,6 @@
 #ifndef CPU_ARM_FRAME_ARM_HPP
 #define CPU_ARM_FRAME_ARM_HPP
 
-#include "runtime/synchronizer.hpp"
-
  public:
   enum {
     pc_return_offset                                 =  0,