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8301153: RISC-V: pipeline class for several instructions is not set c…
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…orrectly

Reviewed-by: fyang, yadongwang
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@feilongjiang @RealFYang
feilongjiang authored and RealFYang committed Jan 31, 2023
1 parent 633e291 commit 9cc0171
Showing 1 changed file with 20 additions and 19 deletions.
39 changes: 20 additions & 19 deletions src/hotspot/cpu/riscv/riscv.ad
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Expand Up @@ -4271,7 +4271,7 @@ pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
%}

// E.g. MUL RD, Rs1, Rs2
pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
%{
single_instruction;
fixed_latency(3); // Maximum latency for 64 bit mul
Expand All @@ -4297,7 +4297,7 @@ pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
%}

// E.g. DIV RD, Rs1, Rs2
pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
%{
single_instruction;
fixed_latency(16); // Maximum latency for 64 bit divide
Expand Down Expand Up @@ -7437,7 +7437,7 @@ instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
__ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
%}

ins_pipe(ialu_reg_reg);
ins_pipe(pipe_class_default);
%}

instruct absL_reg(iRegLNoSp dst, iRegL src) %{
Expand All @@ -7456,7 +7456,7 @@ instruct absL_reg(iRegLNoSp dst, iRegL src) %{
__ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
%}

ins_pipe(ialu_reg_reg);
ins_pipe(pipe_class_default);
%}

instruct absF_reg(fRegF dst, fRegF src) %{
Expand Down Expand Up @@ -7713,7 +7713,7 @@ instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{

instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
match(Set dst (ReverseBytesI src));
effect(TEMP cr);
effect(KILL cr);

ins_cost(ALU_COST * 13);
format %{ "revb_w_w $dst, $src\t#@bytes_reverse_int" %}
Expand All @@ -7722,12 +7722,12 @@ instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
__ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
match(Set dst (ReverseBytesL src));
effect(TEMP cr);
effect(KILL cr);

ins_cost(ALU_COST * 29);
format %{ "revb $dst, $src\t#@bytes_reverse_long" %}
Expand All @@ -7736,7 +7736,7 @@ instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
__ revb(as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
Expand All @@ -7749,7 +7749,7 @@ instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
__ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
Expand All @@ -7762,7 +7762,7 @@ instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
__ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
%}

ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

// ============================================================================
Expand Down Expand Up @@ -8293,7 +8293,7 @@ instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
Register d = $dst$$Register;
__ encode_heap_oop(d, s);
%}
ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
Expand All @@ -8308,7 +8308,7 @@ instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
Register d = $dst$$Register;
__ decode_heap_oop(d, s);
%}
ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
Expand All @@ -8323,7 +8323,7 @@ instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
Register d = $dst$$Register;
__ decode_heap_oop_not_null(d, s);
%}
ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

// Convert klass pointer into compressed form.
Expand All @@ -8339,7 +8339,7 @@ instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
__ encode_klass_not_null(dst_reg, src_reg, t0);
%}

ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
Expand All @@ -8357,7 +8357,7 @@ instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
__ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
%}

ins_pipe(ialu_reg);
ins_pipe(pipe_class_default);
%}

// stack <-> reg and reg <-> reg shuffles with no conversion
Expand Down Expand Up @@ -8394,7 +8394,7 @@ instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
__ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
%}

ins_pipe(pipe_class_memory);
ins_pipe(fp_load_mem_s);

%}

Expand Down Expand Up @@ -8430,7 +8430,7 @@ instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
__ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
%}

ins_pipe(pipe_class_memory);
ins_pipe(fp_load_mem_d);

%}

Expand All @@ -8448,7 +8448,7 @@ instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
__ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
%}

ins_pipe(pipe_class_memory);
ins_pipe(fp_store_reg_s);

%}

Expand Down Expand Up @@ -8484,7 +8484,7 @@ instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
__ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
%}

ins_pipe(pipe_class_memory);
ins_pipe(fp_store_reg_d);

%}

Expand Down Expand Up @@ -8575,6 +8575,7 @@ instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
%}

ins_pipe(fp_l2d);

%}

// ============================================================================
Expand Down

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