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8299327: Allow super late barrier expansion of store barriers in C2
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Reviewed-by: kvn, rcastanedalo
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@fisk
fisk committed Jan 11, 2023
1 parent 257f667 commit f857f8a
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Showing 8 changed files with 29 additions and 14 deletions.
6 changes: 4 additions & 2 deletions src/hotspot/cpu/aarch64/aarch64.ad
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Expand Up @@ -7558,7 +7558,7 @@ instruct storeimmL0(immL0 zero, memory8 mem)
instruct storeP(iRegP src, memory8 mem)
%{
match(Set mem (StoreP mem src));
predicate(!needs_releasing_store(n));
predicate(!needs_releasing_store(n) && n->as_Store()->barrier_data() == 0);

ins_cost(INSN_COST);
format %{ "str $src, $mem\t# ptr" %}
Expand All @@ -7572,7 +7572,7 @@ instruct storeP(iRegP src, memory8 mem)
instruct storeimmP0(immP0 zero, memory8 mem)
%{
match(Set mem (StoreP mem zero));
predicate(!needs_releasing_store(n));
predicate(!needs_releasing_store(n) && n->as_Store()->barrier_data() == 0);

ins_cost(INSN_COST);
format %{ "str zr, $mem\t# ptr" %}
Expand Down Expand Up @@ -7973,6 +7973,7 @@ instruct storeimmL0_volatile(immL0 zero, /* sync_memory*/indirect mem)
instruct storeP_volatile(iRegP src, /* sync_memory*/indirect mem)
%{
match(Set mem (StoreP mem src));
predicate(n->as_Store()->barrier_data() == 0);

ins_cost(VOLATILE_REF_COST);
format %{ "stlr $src, $mem\t# ptr" %}
Expand All @@ -7985,6 +7986,7 @@ instruct storeP_volatile(iRegP src, /* sync_memory*/indirect mem)
instruct storeimmP0_volatile(immP0 zero, /* sync_memory*/indirect mem)
%{
match(Set mem (StoreP mem zero));
predicate(n->as_Store()->barrier_data() == 0);

ins_cost(VOLATILE_REF_COST);
format %{ "stlr zr, $mem\t# ptr" %}
Expand Down
3 changes: 2 additions & 1 deletion src/hotspot/cpu/ppc/ppc.ad
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@@ -1,5 +1,5 @@
//
// Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2011, 2023, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2012, 2022 SAP SE. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
Expand Down Expand Up @@ -6537,6 +6537,7 @@ instruct storeNKlass(memory dst, iRegN_P2N src) %{
// Store Pointer
instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
match(Set dst (StoreP dst src));
predicate(n->as_Store()->barrier_data() == 0);
ins_cost(MEMORY_REF_COST);

format %{ "STD $src, $dst \t// ptr" %}
Expand Down
4 changes: 3 additions & 1 deletion src/hotspot/cpu/riscv/riscv.ad
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@@ -1,5 +1,5 @@
//
// Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
// Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
Expand Down Expand Up @@ -5118,6 +5118,7 @@ instruct storeimmL0(immL0 zero, memory mem)
instruct storeP(iRegP src, memory mem)
%{
match(Set mem (StoreP mem src));
predicate(n->as_Store()->barrier_data() == 0);

ins_cost(STORE_COST);
format %{ "sd $src, $mem\t# ptr, #@storeP" %}
Expand All @@ -5133,6 +5134,7 @@ instruct storeP(iRegP src, memory mem)
instruct storeimmP0(immP0 zero, memory mem)
%{
match(Set mem (StoreP mem zero));
predicate(n->as_Store()->barrier_data() == 0);

ins_cost(STORE_COST);
format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
Expand Down
6 changes: 4 additions & 2 deletions src/hotspot/cpu/x86/x86_64.ad
View file
@@ -1,5 +1,5 @@
//
// Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2003, 2023, Oracle and/or its affiliates. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -6080,6 +6080,7 @@ instruct storeL(memory mem, rRegL src)
// Store Pointer
instruct storeP(memory mem, any_RegP src)
%{
predicate(n->as_Store()->barrier_data() == 0);
match(Set mem (StoreP mem src));

ins_cost(125); // XXX
Expand All @@ -6092,7 +6093,7 @@ instruct storeP(memory mem, any_RegP src)

instruct storeImmP0(memory mem, immP0 zero)
%{
predicate(UseCompressedOops && (CompressedOops::base() == NULL));
predicate(UseCompressedOops && (CompressedOops::base() == NULL) && n->as_Store()->barrier_data() == 0);
match(Set mem (StoreP mem zero));

ins_cost(125); // XXX
Expand All @@ -6106,6 +6107,7 @@ instruct storeImmP0(memory mem, immP0 zero)
// Store NULL Pointer, mark word, or other simple pointer constant.
instruct storeImmP(memory mem, immP31 src)
%{
predicate(n->as_Store()->barrier_data() == 0);
match(Set mem (StoreP mem src));

ins_cost(150); // XXX
Expand Down
3 changes: 2 additions & 1 deletion src/hotspot/share/gc/shared/c2/barrierSetC2.hpp
View file
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2018, 2023, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -264,6 +264,7 @@ class BarrierSetC2: public CHeapObj<mtGC> {
virtual void register_potential_barrier_node(Node* node) const { }
virtual void unregister_potential_barrier_node(Node* node) const { }
virtual void eliminate_gc_barrier(PhaseMacroExpand* macro, Node* node) const { }
virtual void eliminate_gc_barrier_data(Node* node) const { }
virtual void enqueue_useful_gc_barrier(PhaseIterGVN* igvn, Node* node) const {}
virtual void eliminate_useless_gc_barriers(Unique_Node_List &useful, Compile* C) const {}

Expand Down
6 changes: 4 additions & 2 deletions src/hotspot/share/opto/graphKit.cpp
View file
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2001, 2023, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -1550,7 +1550,8 @@ Node* GraphKit::store_to_memory(Node* ctl, Node* adr, Node *val, BasicType bt,
bool require_atomic_access,
bool unaligned,
bool mismatched,
bool unsafe) {
bool unsafe,
int barrier_data) {
assert(adr_idx != Compile::AliasIdxTop, "use other store_to_memory factory" );
const TypePtr* adr_type = NULL;
debug_only(adr_type = C->get_adr_type(adr_idx));
Expand All @@ -1565,6 +1566,7 @@ Node* GraphKit::store_to_memory(Node* ctl, Node* adr, Node *val, BasicType bt,
if (unsafe) {
st->as_Store()->set_unsafe_access();
}
st->as_Store()->set_barrier_data(barrier_data);
st = _gvn.transform(st);
set_memory(st, adr_idx);
// Back-to-back stores can only remove intermediate store with DU info
Expand Down
11 changes: 7 additions & 4 deletions src/hotspot/share/opto/graphKit.hpp
View file
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2001, 2023, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -568,13 +568,15 @@ class GraphKit : public Phase {
bool require_atomic_access = false,
bool unaligned = false,
bool mismatched = false,
bool unsafe = false) {
bool unsafe = false,
int barrier_data = 0) {
// This version computes alias_index from an address type
assert(adr_type != NULL, "use other store_to_memory factory");
return store_to_memory(ctl, adr, val, bt,
C->get_alias_index(adr_type),
mo, require_atomic_access,
unaligned, mismatched, unsafe);
unaligned, mismatched, unsafe,
barrier_data);
}
// This is the base version which is given alias index
// Return the new StoreXNode
Expand All @@ -584,7 +586,8 @@ class GraphKit : public Phase {
bool require_atomic_access = false,
bool unaligned = false,
bool mismatched = false,
bool unsafe = false);
bool unsafe = false,
int barrier_data = 0);

// Perform decorated accesses

Expand Down
4 changes: 3 additions & 1 deletion src/hotspot/share/opto/memnode.cpp
View file
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -4004,9 +4004,11 @@ Node* InitializeNode::capture_store(StoreNode* st, intptr_t start,
ins_req(i, C->top()); // build a new edge
}
Node* new_st = st->clone();
BarrierSetC2* bs = BarrierSet::barrier_set()->barrier_set_c2();
new_st->set_req(MemNode::Control, in(Control));
new_st->set_req(MemNode::Memory, prev_mem);
new_st->set_req(MemNode::Address, make_raw_address(start, phase));
bs->eliminate_gc_barrier_data(new_st);
new_st = phase->transform(new_st);

// At this point, new_st might have swallowed a pre-existing store
Expand Down

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