8296515: RISC-V: Small refactoring for MaxReductionV/MinReductionV/Ad…

…dReductionV node implementation Reviewed-by: luhenry, dzhang, yzhu, fyang
openjdk · Nov 9, 2022 · fef68bb · fef68bb · openjdk-notifier · Nov 9, 2022
1 parent 82cbfb5
commit fef68bb
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Showing 4 changed files with 73 additions and 169 deletions.
diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -1690,27 +1690,36 @@ bool C2_MacroAssembler::in_scratch_emit_size() {
   return MacroAssembler::in_scratch_emit_size();
 }
 
-void C2_MacroAssembler::reduce_operation(Register dst, VectorRegister tmp,
-                                         Register src1, VectorRegister src2,
-                                         BasicType bt, REDUCTION_OP op) {
+void C2_MacroAssembler::rvv_reduce_integral(Register dst, VectorRegister tmp,
+                                            Register src1, VectorRegister src2,
+                                            BasicType bt, int opc) {
+  assert(bt == T_BYTE || bt == T_SHORT || bt == T_INT || bt == T_LONG, "unsupported element type");
+
   Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
   vsetvli(t0, x0, sew);
 
   vmv_s_x(tmp, src1);
 
-  switch (op) {
-    case REDUCTION_OP::ADD:
+  switch (opc) {
+    case Op_AddReductionVI:
+    case Op_AddReductionVL:
       vredsum_vs(tmp, src2, tmp);
       break;
-    case REDUCTION_OP::AND:
+    case Op_AndReductionV:
       vredand_vs(tmp, src2, tmp);
       break;
-    case REDUCTION_OP::OR:
+    case Op_OrReductionV:
       vredor_vs(tmp, src2, tmp);
       break;
-    case REDUCTION_OP::XOR:
+    case Op_XorReductionV:
       vredxor_vs(tmp, src2, tmp);
       break;
+    case Op_MaxReductionV:
+      vredmax_vs(tmp, src2, tmp);
+      break;
+    case Op_MinReductionV:
+      vredmin_vs(tmp, src2, tmp);
+      break;
     default:
       ShouldNotReachHere();
   }

diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
@@ -195,8 +195,8 @@
                          VectorRegister tmp1, VectorRegister tmp2,
                          bool is_double, bool is_min);
 
- void reduce_operation(Register dst, VectorRegister tmp,
-                       Register src1, VectorRegister src2,
-                       BasicType bt, REDUCTION_OP op);
+ void rvv_reduce_integral(Register dst, VectorRegister tmp,
+                          Register src1, VectorRegister src2,
+                          BasicType bt, int opc);
 
 #endif // CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP
diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
@@ -1300,7 +1300,4 @@ class SkipIfEqual {
    ~SkipIfEqual();
 };
 
-// reduction related operations
-enum REDUCTION_OP {ADD, AND, OR, XOR};
-
 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP