c2_MacroAssembler_aarch64.hpp

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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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#ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
#define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

// C2_MacroAssembler contains high-level macros for C2

 public:

  void string_compare(Register str1, Register str2,
                      Register cnt1, Register cnt2, Register result,
                      Register tmp1, Register tmp2, FloatRegister vtmp1,
                      FloatRegister vtmp2, FloatRegister vtmp3,
                      PRegister pgtmp1, PRegister pgtmp2, int ae);

  void string_indexof(Register str1, Register str2,
                      Register cnt1, Register cnt2,
                      Register tmp1, Register tmp2,
                      Register tmp3, Register tmp4,
                      Register tmp5, Register tmp6,
                      int int_cnt1, Register result, int ae);

  void string_indexof_char(Register str1, Register cnt1,
                           Register ch, Register result,
                           Register tmp1, Register tmp2, Register tmp3);

  void stringL_indexof_char(Register str1, Register cnt1,
                            Register ch, Register result,
                            Register tmp1, Register tmp2, Register tmp3);

  void string_indexof_char_sve(Register str1, Register cnt1,
                               Register ch, Register result,
                               FloatRegister ztmp1, FloatRegister ztmp2,
                               PRegister pgtmp, PRegister ptmp, bool isL);

  // Compress the least significant bit of each byte to the rightmost and clear
  // the higher garbage bits.
  void bytemask_compress(Register dst);

  // Pack the lowest-numbered bit of each mask element in src into a long value
  // in dst, at most the first 64 lane elements.
  void sve_vmask_tolong(Register dst, PRegister src, BasicType bt, int lane_cnt,
                        FloatRegister vtmp1, FloatRegister vtmp2, PRegister pgtmp);

  // SIMD&FP comparison
  void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
                    FloatRegister src2, int cond, bool isQ);

  void sve_compare(PRegister pd, BasicType bt, PRegister pg,
                   FloatRegister zn, FloatRegister zm, int cond);

  void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);

  void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
                         FloatRegister src, SIMD_RegVariant src_size);

  void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
                         FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);

  void sve_vmaskcast_extend(PRegister dst, PRegister src,
                            uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);

  void sve_vmaskcast_narrow(PRegister dst, PRegister src,
                            uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);

  void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
                           FloatRegister src2, PRegister pg, FloatRegister tmp);

  // Set elements of the dst predicate to true if the element number is
  // in the range of [0, lane_cnt), or to false otherwise.
  void sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt);

  // Generate predicate through whilelo, by comparing ZR with an unsigned
  // immediate. rscratch1 will be clobbered.
  inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {
    assert(UseSVE > 0, "not supported");
    mov(rscratch1, imm);
    sve_whilelo(pd, size, zr, rscratch1);
  }

  // Extract a scalar element from an sve vector at position 'idx'.
  // rscratch1 will be clobbered.
  // T could be FloatRegister or Register.
  template<class T>
  inline void sve_extract(T dst, SIMD_RegVariant size, PRegister pg, FloatRegister src, int idx) {
    assert(UseSVE > 0, "not supported");
    assert(pg->is_governing(), "This register has to be a governing predicate register");
    mov(rscratch1, idx);
    sve_whilele(pg, size, zr, rscratch1);
    sve_lastb(dst, size, pg, src);
  }

#endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP