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c1_LIRAssembler_ppc.cpp
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c1_LIRAssembler_ppc.cpp
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/*
* Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2019, SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_LIRAssembler.hpp"
#include "c1/c1_MacroAssembler.hpp"
#include "c1/c1_Runtime1.hpp"
#include "c1/c1_ValueStack.hpp"
#include "ci/ciArrayKlass.hpp"
#include "ci/ciInstance.hpp"
#include "gc/shared/collectedHeap.hpp"
#include "memory/universe.hpp"
#include "nativeInst_ppc.hpp"
#include "oops/compressedOops.hpp"
#include "oops/objArrayKlass.hpp"
#include "runtime/frame.inline.hpp"
#include "runtime/safepointMechanism.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "utilities/powerOfTwo.hpp"
#define __ _masm->
const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
Unimplemented(); return false; // Currently not used on this platform.
}
LIR_Opr LIR_Assembler::receiverOpr() {
return FrameMap::R3_oop_opr;
}
LIR_Opr LIR_Assembler::osrBufferPointer() {
return FrameMap::R3_opr;
}
// This specifies the stack pointer decrement needed to build the frame.
int LIR_Assembler::initial_frame_size_in_bytes() const {
return in_bytes(frame_map()->framesize_in_bytes());
}
// Inline cache check: the inline cached class is in inline_cache_reg;
// we fetch the class of the receiver and compare it with the cached class.
// If they do not match we jump to slow case.
int LIR_Assembler::check_icache() {
int offset = __ offset();
__ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
return offset;
}
void LIR_Assembler::clinit_barrier(ciMethod* method) {
assert(!method->holder()->is_not_initialized(), "initialization should have been started");
Label L_skip_barrier;
Register klass = R20;
metadata2reg(method->holder()->constant_encoding(), klass);
__ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
__ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
__ mtctr(klass);
__ bctr();
__ bind(L_skip_barrier);
}
void LIR_Assembler::osr_entry() {
// On-stack-replacement entry sequence:
//
// 1. Create a new compiled activation.
// 2. Initialize local variables in the compiled activation. The expression
// stack must be empty at the osr_bci; it is not initialized.
// 3. Jump to the continuation address in compiled code to resume execution.
// OSR entry point
offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
BlockBegin* osr_entry = compilation()->hir()->osr_entry();
ValueStack* entry_state = osr_entry->end()->state();
int number_of_locks = entry_state->locks_size();
// Create a frame for the compiled activation.
__ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
// OSR buffer is
//
// locals[nlocals-1..0]
// monitors[number_of_locks-1..0]
//
// Locals is a direct copy of the interpreter frame so in the osr buffer
// the first slot in the local array is the last local from the interpreter
// and the last slot is local[0] (receiver) from the interpreter.
//
// Similarly with locks. The first lock slot in the osr buffer is the nth lock
// from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
// in the interpreter frame (the method lock if a sync method).
// Initialize monitors in the compiled activation.
// R3: pointer to osr buffer
//
// All other registers are dead at this point and the locals will be
// copied into place by code emitted in the IR.
Register OSR_buf = osrBufferPointer()->as_register();
{ assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
int monitor_offset = BytesPerWord * method()->max_locals() +
(2 * BytesPerWord) * (number_of_locks - 1);
// SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
// the OSR buffer using 2 word entries: first the lock and then
// the oop.
for (int i = 0; i < number_of_locks; i++) {
int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
#ifdef ASSERT
// Verify the interpreter's monitor has a non-null object.
{
Label L;
__ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
__ cmpdi(CCR0, R0, 0);
__ bne(CCR0, L);
__ stop("locked object is NULL");
__ bind(L);
}
#endif // ASSERT
// Copy the lock field into the compiled activation.
Address ml = frame_map()->address_for_monitor_lock(i),
mo = frame_map()->address_for_monitor_object(i);
assert(ml.index() == noreg && mo.index() == noreg, "sanity");
__ ld(R0, slot_offset + 0, OSR_buf);
__ std(R0, ml.disp(), ml.base());
__ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
__ std(R0, mo.disp(), mo.base());
}
}
}
int LIR_Assembler::emit_exception_handler() {
// If the last instruction is a call (typically to do a throw which
// is coming at the end after block reordering) the return address
// must still point into the code area in order to avoid assertion
// failures when searching for the corresponding bci => add a nop
// (was bug 5/14/1999 - gri).
__ nop();
// Generate code for the exception handler.
address handler_base = __ start_a_stub(exception_handler_size());
if (handler_base == NULL) {
// Not enough space left for the handler.
bailout("exception handler overflow");
return -1;
}
int offset = code_offset();
address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
//__ load_const_optimized(R0, entry_point);
__ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
__ mtctr(R0);
__ bctr();
guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
__ end_a_stub();
return offset;
}
// Emit the code to remove the frame from the stack in the exception
// unwind path.
int LIR_Assembler::emit_unwind_handler() {
_masm->block_comment("Unwind handler");
int offset = code_offset();
bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
// Fetch the exception from TLS and clear out exception related thread state.
__ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
__ li(R0, 0);
__ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
__ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
__ bind(_unwind_handler_entry);
__ verify_not_null_oop(Rexception);
if (preserve_exception) { __ mr(Rexception_save, Rexception); }
// Perform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::R4_opr);
stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
__ unlock_object(R5, R6, R4, *stub->entry());
__ bind(*stub->continuation());
}
if (compilation()->env()->dtrace_method_probes()) {
Unimplemented();
}
// Dispatch to the unwind logic.
address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
//__ load_const_optimized(R0, unwind_stub);
__ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
if (preserve_exception) { __ mr(Rexception, Rexception_save); }
__ mtctr(R0);
__ bctr();
// Emit the slow path assembly.
if (stub != NULL) {
stub->emit_code(this);
}
return offset;
}
int LIR_Assembler::emit_deopt_handler() {
// If the last instruction is a call (typically to do a throw which
// is coming at the end after block reordering) the return address
// must still point into the code area in order to avoid assertion
// failures when searching for the corresponding bci => add a nop
// (was bug 5/14/1999 - gri).
__ nop();
// Generate code for deopt handler.
address handler_base = __ start_a_stub(deopt_handler_size());
if (handler_base == NULL) {
// Not enough space left for the handler.
bailout("deopt handler overflow");
return -1;
}
int offset = code_offset();
__ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
__ end_a_stub();
return offset;
}
void LIR_Assembler::jobject2reg(jobject o, Register reg) {
if (o == NULL) {
__ li(reg, 0);
} else {
AddressLiteral addrlit = __ constant_oop_address(o);
__ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
}
}
void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
// Allocate a new index in table to hold the object once it's been patched.
int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
__ load_const(reg, addrlit, R0);
patching_epilog(patch, lir_patch_normal, reg, info);
}
void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
__ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
}
void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
// Allocate a new index in table to hold the klass once it's been patched.
int index = __ oop_recorder()->allocate_metadata_index(NULL);
PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
__ load_const(reg, addrlit, R0);
patching_epilog(patch, lir_patch_normal, reg, info);
}
void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
const bool is_int = result->is_single_cpu();
Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
Register Rdivisor = noreg;
Register Rscratch = temp->as_register();
Register Rresult = is_int ? result->as_register() : result->as_register_lo();
long divisor = -1;
if (right->is_register()) {
Rdivisor = is_int ? right->as_register() : right->as_register_lo();
} else {
divisor = is_int ? right->as_constant_ptr()->as_jint()
: right->as_constant_ptr()->as_jlong();
}
assert(Rdividend != Rscratch, "");
assert(Rdivisor != Rscratch, "");
assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
if (Rdivisor == noreg) {
if (divisor == 1) { // stupid, but can happen
if (code == lir_idiv) {
__ mr_if_needed(Rresult, Rdividend);
} else {
__ li(Rresult, 0);
}
} else if (is_power_of_2(divisor)) {
// Convert division by a power of two into some shifts and logical operations.
int log2 = log2_intptr(divisor);
// Round towards 0.
if (divisor == 2) {
if (is_int) {
__ srwi(Rscratch, Rdividend, 31);
} else {
__ srdi(Rscratch, Rdividend, 63);
}
} else {
if (is_int) {
__ srawi(Rscratch, Rdividend, 31);
} else {
__ sradi(Rscratch, Rdividend, 63);
}
__ clrldi(Rscratch, Rscratch, 64-log2);
}
__ add(Rscratch, Rdividend, Rscratch);
if (code == lir_idiv) {
if (is_int) {
__ srawi(Rresult, Rscratch, log2);
} else {
__ sradi(Rresult, Rscratch, log2);
}
} else { // lir_irem
__ clrrdi(Rscratch, Rscratch, log2);
__ sub(Rresult, Rdividend, Rscratch);
}
} else if (divisor == -1) {
if (code == lir_idiv) {
__ neg(Rresult, Rdividend);
} else {
__ li(Rresult, 0);
}
} else {
__ load_const_optimized(Rscratch, divisor);
if (code == lir_idiv) {
if (is_int) {
__ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
} else {
__ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
}
} else {
assert(Rscratch != R0, "need both");
if (is_int) {
__ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
__ mullw(Rscratch, R0, Rscratch);
} else {
__ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
__ mulld(Rscratch, R0, Rscratch);
}
__ sub(Rresult, Rdividend, Rscratch);
}
}
return;
}
Label regular, done;
if (is_int) {
__ cmpwi(CCR0, Rdivisor, -1);
} else {
__ cmpdi(CCR0, Rdivisor, -1);
}
__ bne(CCR0, regular);
if (code == lir_idiv) {
__ neg(Rresult, Rdividend);
__ b(done);
__ bind(regular);
if (is_int) {
__ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
} else {
__ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
}
} else { // lir_irem
__ li(Rresult, 0);
__ b(done);
__ bind(regular);
if (is_int) {
__ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
__ mullw(Rscratch, Rscratch, Rdivisor);
} else {
__ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
__ mulld(Rscratch, Rscratch, Rdivisor);
}
__ sub(Rresult, Rdividend, Rscratch);
}
__ bind(done);
}
void LIR_Assembler::emit_op3(LIR_Op3* op) {
switch (op->code()) {
case lir_idiv:
case lir_irem:
arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
op->result_opr(), op->info());
break;
case lir_fmad:
__ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
break;
case lir_fmaf:
__ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
break;
default: ShouldNotReachHere(); break;
}
}
void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
#ifdef ASSERT
assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
if (op->block() != NULL) _branch_target_blocks.append(op->block());
if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
#endif
Label *L = op->label();
if (op->cond() == lir_cond_always) {
__ b(*L);
} else {
Label done;
bool is_unordered = false;
if (op->code() == lir_cond_float_branch) {
assert(op->ublock() != NULL, "must have unordered successor");
is_unordered = true;
} else {
assert(op->code() == lir_branch, "just checking");
}
bool positive = false;
Assembler::Condition cond = Assembler::equal;
switch (op->cond()) {
case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
case lir_cond_less: positive = true ; cond = Assembler::less ; break;
case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
default: ShouldNotReachHere();
}
int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
int bi = Assembler::bi0(BOOL_RESULT, cond);
if (is_unordered) {
if (positive) {
if (op->ublock() == op->block()) {
__ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
}
} else {
if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
}
}
__ bc_far_optimized(bo, bi, *L);
__ bind(done);
}
}
void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
Bytecodes::Code code = op->bytecode();
LIR_Opr src = op->in_opr(),
dst = op->result_opr();
switch(code) {
case Bytecodes::_i2l: {
__ extsw(dst->as_register_lo(), src->as_register());
break;
}
case Bytecodes::_l2i: {
__ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
break;
}
case Bytecodes::_i2b: {
__ extsb(dst->as_register(), src->as_register());
break;
}
case Bytecodes::_i2c: {
__ clrldi(dst->as_register(), src->as_register(), 64-16);
break;
}
case Bytecodes::_i2s: {
__ extsh(dst->as_register(), src->as_register());
break;
}
case Bytecodes::_i2d:
case Bytecodes::_l2d: {
bool src_in_memory = !VM_Version::has_mtfprd();
FloatRegister rdst = dst->as_double_reg();
FloatRegister rsrc;
if (src_in_memory) {
rsrc = src->as_double_reg(); // via mem
} else {
// move src to dst register
if (code == Bytecodes::_i2d) {
__ mtfprwa(rdst, src->as_register());
} else {
__ mtfprd(rdst, src->as_register_lo());
}
rsrc = rdst;
}
__ fcfid(rdst, rsrc);
break;
}
case Bytecodes::_i2f:
case Bytecodes::_l2f: {
bool src_in_memory = !VM_Version::has_mtfprd();
FloatRegister rdst = dst->as_float_reg();
FloatRegister rsrc;
if (src_in_memory) {
rsrc = src->as_double_reg(); // via mem
} else {
// move src to dst register
if (code == Bytecodes::_i2f) {
__ mtfprwa(rdst, src->as_register());
} else {
__ mtfprd(rdst, src->as_register_lo());
}
rsrc = rdst;
}
if (VM_Version::has_fcfids()) {
__ fcfids(rdst, rsrc);
} else {
assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
__ fcfid(rdst, rsrc);
__ frsp(rdst, rdst);
}
break;
}
case Bytecodes::_f2d: {
__ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
break;
}
case Bytecodes::_d2f: {
__ frsp(dst->as_float_reg(), src->as_double_reg());
break;
}
case Bytecodes::_d2i:
case Bytecodes::_f2i: {
bool dst_in_memory = !VM_Version::has_mtfprd();
FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
Label L;
// Result must be 0 if value is NaN; test by comparing value to itself.
__ fcmpu(CCR0, rsrc, rsrc);
if (dst_in_memory) {
__ li(R0, 0); // 0 in case of NAN
__ std(R0, addr.disp(), addr.base());
} else {
__ li(dst->as_register(), 0);
}
__ bso(CCR0, L);
__ fctiwz(rsrc, rsrc); // USE_KILL
if (dst_in_memory) {
__ stfd(rsrc, addr.disp(), addr.base());
} else {
__ mffprd(dst->as_register(), rsrc);
}
__ bind(L);
break;
}
case Bytecodes::_d2l:
case Bytecodes::_f2l: {
bool dst_in_memory = !VM_Version::has_mtfprd();
FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
Label L;
// Result must be 0 if value is NaN; test by comparing value to itself.
__ fcmpu(CCR0, rsrc, rsrc);
if (dst_in_memory) {
__ li(R0, 0); // 0 in case of NAN
__ std(R0, addr.disp(), addr.base());
} else {
__ li(dst->as_register_lo(), 0);
}
__ bso(CCR0, L);
__ fctidz(rsrc, rsrc); // USE_KILL
if (dst_in_memory) {
__ stfd(rsrc, addr.disp(), addr.base());
} else {
__ mffprd(dst->as_register_lo(), rsrc);
}
__ bind(L);
break;
}
default: ShouldNotReachHere();
}
}
void LIR_Assembler::align_call(LIR_Code) {
// do nothing since all instructions are word aligned on ppc
}
bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
int start_offset = __ offset();
// Put the entry point as a constant into the constant pool.
const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
if (entry_point_toc_addr == NULL) {
bailout("const section overflow");
return false;
}
const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
// Emit the trampoline stub which will be related to the branch-and-link below.
address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
if (!stub) {
bailout("no space for trampoline stub");
return false;
}
return true;
}
void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
bool success = emit_trampoline_stub_for_call(op->addr());
if (!success) { return; }
__ relocate(rtype);
// Note: At this point we do not have the address of the trampoline
// stub, and the entry point might be too far away for bl, so __ pc()
// serves as dummy and the bl will be patched later.
__ code()->set_insts_mark();
__ bl(__ pc());
add_call_info(code_offset(), op->info());
}
void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
__ calculate_address_from_global_toc(R2_TOC, __ method_toc());
// Virtual call relocation will point to ic load.
address virtual_call_meta_addr = __ pc();
// Load a clear inline cache.
AddressLiteral empty_ic((address) Universe::non_oop_word());
bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
if (!success) {
bailout("const section overflow");
return;
}
// Call to fixup routine. Fixup routine uses ScopeDesc info
// to determine who we intended to call.
__ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
if (!success) { return; }
// Note: At this point we do not have the address of the trampoline
// stub, and the entry point might be too far away for bl, so __ pc()
// serves as dummy and the bl will be patched later.
__ bl(__ pc());
add_call_info(code_offset(), op->info());
}
void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
ShouldNotReachHere(); // ic_call is used instead.
}
void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
__ null_check(addr, stub->entry());
append_code_stub(stub);
}
// Attention: caller must encode oop if needed
int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
int store_offset;
if (!Assembler::is_simm16(offset)) {
// For offsets larger than a simm16 we setup the offset.
assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
__ load_const_optimized(R0, offset);
store_offset = store(from_reg, base, R0, type, wide);
} else {
store_offset = code_offset();
switch (type) {
case T_BOOLEAN: // fall through
case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
case T_CHAR :
case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
case T_INT : __ stw(from_reg->as_register(), offset, base); break;
case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
case T_ADDRESS:
case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
case T_ARRAY : // fall through
case T_OBJECT:
{
if (UseCompressedOops && !wide) {
// Encoding done in caller
__ stw(from_reg->as_register(), offset, base);
__ verify_coop(from_reg->as_register(), FILE_AND_LINE);
} else {
__ std(from_reg->as_register(), offset, base);
__ verify_oop(from_reg->as_register(), FILE_AND_LINE);
}
break;
}
case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
default : ShouldNotReachHere();
}
}
return store_offset;
}
// Attention: caller must encode oop if needed
int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
int store_offset = code_offset();
switch (type) {
case T_BOOLEAN: // fall through
case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
case T_CHAR :
case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
case T_LONG :
#ifdef _LP64
__ stdx(from_reg->as_register_lo(), base, disp);
#else
Unimplemented();
#endif
break;
case T_ADDRESS:
__ stdx(from_reg->as_register(), base, disp);
break;
case T_ARRAY : // fall through
case T_OBJECT:
{
if (UseCompressedOops && !wide) {
// Encoding done in caller.
__ stwx(from_reg->as_register(), base, disp);
__ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
} else {
__ stdx(from_reg->as_register(), base, disp);
__ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
}
break;
}
case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
default : ShouldNotReachHere();
}
return store_offset;
}
int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
int load_offset;
if (!Assembler::is_simm16(offset)) {
// For offsets larger than a simm16 we setup the offset.
__ load_const_optimized(R0, offset);
load_offset = load(base, R0, to_reg, type, wide);
} else {
load_offset = code_offset();
switch(type) {
case T_BOOLEAN: // fall through
case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
__ extsb(to_reg->as_register(), to_reg->as_register()); break;
case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
case T_ADDRESS:
if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
__ lwz(to_reg->as_register(), offset, base);
__ decode_klass_not_null(to_reg->as_register());
} else {
__ ld(to_reg->as_register(), offset, base);
}
break;
case T_ARRAY : // fall through
case T_OBJECT:
{
if (UseCompressedOops && !wide) {
__ lwz(to_reg->as_register(), offset, base);
__ decode_heap_oop(to_reg->as_register());
} else {
__ ld(to_reg->as_register(), offset, base);
}
__ verify_oop(to_reg->as_register(), FILE_AND_LINE);
break;
}
case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
default : ShouldNotReachHere();
}
}
return load_offset;
}
int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
int load_offset = code_offset();
switch(type) {
case T_BOOLEAN: // fall through
case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
__ extsb(to_reg->as_register(), to_reg->as_register()); break;
case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
case T_ARRAY : // fall through
case T_OBJECT:
{
if (UseCompressedOops && !wide) {
__ lwzx(to_reg->as_register(), base, disp);
__ decode_heap_oop(to_reg->as_register());
} else {
__ ldx(to_reg->as_register(), base, disp);
}
__ verify_oop(to_reg->as_register(), FILE_AND_LINE);
break;
}
case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
case T_LONG :
#ifdef _LP64
__ ldx(to_reg->as_register_lo(), base, disp);
#else
Unimplemented();
#endif
break;
default : ShouldNotReachHere();
}
return load_offset;
}
void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
LIR_Const* c = src->as_constant_ptr();
Register src_reg = R0;
switch (c->type()) {
case T_INT:
case T_FLOAT: {
int value = c->as_jint_bits();
__ load_const_optimized(src_reg, value);
Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
__ stw(src_reg, addr.disp(), addr.base());
break;
}
case T_ADDRESS: {
int value = c->as_jint_bits();
__ load_const_optimized(src_reg, value);
Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
__ std(src_reg, addr.disp(), addr.base());
break;
}
case T_OBJECT: {
jobject2reg(c->as_jobject(), src_reg);
Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
__ std(src_reg, addr.disp(), addr.base());
break;
}
case T_LONG:
case T_DOUBLE: {
int value = c->as_jlong_bits();
__ load_const_optimized(src_reg, value);
Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
__ std(src_reg, addr.disp(), addr.base());
break;
}
default:
Unimplemented();
}
}
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
LIR_Const* c = src->as_constant_ptr();
LIR_Address* addr = dest->as_address_ptr();
Register base = addr->base()->as_pointer_register();
LIR_Opr tmp = LIR_OprFact::illegalOpr;
int offset = -1;
// Null check for large offsets in LIRGenerator::do_StoreField.
bool needs_explicit_null_check = !ImplicitNullChecks;
if (info != NULL && needs_explicit_null_check) {
explicit_null_check(base, info);
}
switch (c->type()) {
case T_FLOAT: type = T_INT;
case T_INT:
case T_ADDRESS: {
tmp = FrameMap::R0_opr;
__ load_const_optimized(tmp->as_register(), c->as_jint_bits());
break;
}
case T_DOUBLE: type = T_LONG;
case T_LONG: {
tmp = FrameMap::R0_long_opr;
__ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
break;
}
case T_OBJECT: {
tmp = FrameMap::R0_opr;
if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
__ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
__ relocate(oop_addr.rspec(), /*compressed format*/ 1);
__ ori(R0, R0, oop_addr.value() & 0xffff);
} else {
jobject2reg(c->as_jobject(), R0);
}
break;
}
default:
Unimplemented();
}
// Handle either reg+reg or reg+disp address.
if (addr->index()->is_valid()) {
assert(addr->disp() == 0, "must be zero");
offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
} else {
assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
offset = store(tmp, base, addr->disp(), type, wide, false);
}
if (info != NULL) {
assert(offset != -1, "offset should've been set");
if (!needs_explicit_null_check) {
add_debug_info_for_null_check(offset, info);
}
}
}
void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
LIR_Const* c = src->as_constant_ptr();
LIR_Opr to_reg = dest;
switch (c->type()) {
case T_INT: {
assert(patch_code == lir_patch_none, "no patching handled here");
__ load_const_optimized(dest->as_register(), c->as_jint(), R0);
break;
}
case T_ADDRESS: {
assert(patch_code == lir_patch_none, "no patching handled here");
__ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
break;
}
case T_LONG: {
assert(patch_code == lir_patch_none, "no patching handled here");