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//
// Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2012, 2019 SAP SE. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
//
// PPC64 Architecture Description File
//
//----------REGISTER DEFINITION BLOCK------------------------------------------
// This information is used by the matcher and the register allocator to
// describe individual registers and classes of registers within the target
// architecture.
register %{
//----------Architecture Description Register Definitions----------------------
// General Registers
// "reg_def" name (register save type, C convention save type,
// ideal register type, encoding);
//
// Register Save Types:
//
// NS = No-Save: The register allocator assumes that these registers
// can be used without saving upon entry to the method, &
// that they do not need to be saved at call sites.
//
// SOC = Save-On-Call: The register allocator assumes that these registers
// can be used without saving upon entry to the method,
// but that they must be saved at call sites.
// These are called "volatiles" on ppc.
//
// SOE = Save-On-Entry: The register allocator assumes that these registers
// must be saved before using them upon entry to the
// method, but they do not need to be saved at call
// sites.
// These are called "nonvolatiles" on ppc.
//
// AS = Always-Save: The register allocator assumes that these registers
// must be saved before using them upon entry to the
// method, & that they must be saved at call sites.
//
// Ideal Register Type is used to determine how to save & restore a
// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
// spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
//
// The encoding number is the actual bit-pattern placed into the opcodes.
//
// PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
// Supplement Version 1.7 as of 2003-10-29.
//
// For each 64-bit register we must define two registers: the register
// itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
// e.g. R3_H, which is needed by the allocator, but is not used
// for stores, loads, etc.
// ----------------------------
// Integer/Long Registers
// ----------------------------
// PPC64 has 32 64-bit integer registers.
// types: v = volatile, nv = non-volatile, s = system
reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
// ----------------------------
// Float/Double Registers
// ----------------------------
// Double Registers
// The rules of ADL require that double registers be defined in pairs.
// Each pair must be two 32-bit values, but not necessarily a pair of
// single float registers. In each pair, ADLC-assigned register numbers
// must be adjacent, with the lower number even. Finally, when the
// CPU stores such a register pair to memory, the word associated with
// the lower ADLC-assigned number must be stored to the lower address.
// PPC64 has 32 64-bit floating-point registers. Each can store a single
// or double precision floating-point value.
// types: v = volatile, nv = non-volatile, s = system
reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
// ----------------------------
// Special Registers
// ----------------------------
// Condition Codes Flag Registers
// PPC64 has 8 condition code "registers" which are all contained
// in the CR register.
// types: v = volatile, nv = non-volatile, s = system
reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
// Special registers of PPC64
reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
// ----------------------------
// Vector-Scalar Registers
// ----------------------------
reg_def VSR0 ( SOC, SOC, Op_VecX, 0, NULL);
reg_def VSR1 ( SOC, SOC, Op_VecX, 1, NULL);
reg_def VSR2 ( SOC, SOC, Op_VecX, 2, NULL);
reg_def VSR3 ( SOC, SOC, Op_VecX, 3, NULL);
reg_def VSR4 ( SOC, SOC, Op_VecX, 4, NULL);
reg_def VSR5 ( SOC, SOC, Op_VecX, 5, NULL);
reg_def VSR6 ( SOC, SOC, Op_VecX, 6, NULL);
reg_def VSR7 ( SOC, SOC, Op_VecX, 7, NULL);
reg_def VSR8 ( SOC, SOC, Op_VecX, 8, NULL);
reg_def VSR9 ( SOC, SOC, Op_VecX, 9, NULL);
reg_def VSR10 ( SOC, SOC, Op_VecX, 10, NULL);
reg_def VSR11 ( SOC, SOC, Op_VecX, 11, NULL);
reg_def VSR12 ( SOC, SOC, Op_VecX, 12, NULL);
reg_def VSR13 ( SOC, SOC, Op_VecX, 13, NULL);
reg_def VSR14 ( SOC, SOC, Op_VecX, 14, NULL);
reg_def VSR15 ( SOC, SOC, Op_VecX, 15, NULL);
reg_def VSR16 ( SOC, SOC, Op_VecX, 16, NULL);
reg_def VSR17 ( SOC, SOC, Op_VecX, 17, NULL);
reg_def VSR18 ( SOC, SOC, Op_VecX, 18, NULL);
reg_def VSR19 ( SOC, SOC, Op_VecX, 19, NULL);
reg_def VSR20 ( SOC, SOC, Op_VecX, 20, NULL);
reg_def VSR21 ( SOC, SOC, Op_VecX, 21, NULL);
reg_def VSR22 ( SOC, SOC, Op_VecX, 22, NULL);
reg_def VSR23 ( SOC, SOC, Op_VecX, 23, NULL);
reg_def VSR24 ( SOC, SOC, Op_VecX, 24, NULL);
reg_def VSR25 ( SOC, SOC, Op_VecX, 25, NULL);
reg_def VSR26 ( SOC, SOC, Op_VecX, 26, NULL);
reg_def VSR27 ( SOC, SOC, Op_VecX, 27, NULL);
reg_def VSR28 ( SOC, SOC, Op_VecX, 28, NULL);
reg_def VSR29 ( SOC, SOC, Op_VecX, 29, NULL);
reg_def VSR30 ( SOC, SOC, Op_VecX, 30, NULL);
reg_def VSR31 ( SOC, SOC, Op_VecX, 31, NULL);
reg_def VSR32 ( SOC, SOC, Op_VecX, 32, NULL);
reg_def VSR33 ( SOC, SOC, Op_VecX, 33, NULL);
reg_def VSR34 ( SOC, SOC, Op_VecX, 34, NULL);
reg_def VSR35 ( SOC, SOC, Op_VecX, 35, NULL);
reg_def VSR36 ( SOC, SOC, Op_VecX, 36, NULL);
reg_def VSR37 ( SOC, SOC, Op_VecX, 37, NULL);
reg_def VSR38 ( SOC, SOC, Op_VecX, 38, NULL);
reg_def VSR39 ( SOC, SOC, Op_VecX, 39, NULL);
reg_def VSR40 ( SOC, SOC, Op_VecX, 40, NULL);
reg_def VSR41 ( SOC, SOC, Op_VecX, 41, NULL);
reg_def VSR42 ( SOC, SOC, Op_VecX, 42, NULL);
reg_def VSR43 ( SOC, SOC, Op_VecX, 43, NULL);
reg_def VSR44 ( SOC, SOC, Op_VecX, 44, NULL);
reg_def VSR45 ( SOC, SOC, Op_VecX, 45, NULL);
reg_def VSR46 ( SOC, SOC, Op_VecX, 46, NULL);
reg_def VSR47 ( SOC, SOC, Op_VecX, 47, NULL);
reg_def VSR48 ( SOC, SOC, Op_VecX, 48, NULL);
reg_def VSR49 ( SOC, SOC, Op_VecX, 49, NULL);
reg_def VSR50 ( SOC, SOC, Op_VecX, 50, NULL);
reg_def VSR51 ( SOC, SOC, Op_VecX, 51, NULL);
reg_def VSR52 ( SOC, SOC, Op_VecX, 52, NULL);
reg_def VSR53 ( SOC, SOC, Op_VecX, 53, NULL);
reg_def VSR54 ( SOC, SOC, Op_VecX, 54, NULL);
reg_def VSR55 ( SOC, SOC, Op_VecX, 55, NULL);
reg_def VSR56 ( SOC, SOC, Op_VecX, 56, NULL);
reg_def VSR57 ( SOC, SOC, Op_VecX, 57, NULL);
reg_def VSR58 ( SOC, SOC, Op_VecX, 58, NULL);
reg_def VSR59 ( SOC, SOC, Op_VecX, 59, NULL);
reg_def VSR60 ( SOC, SOC, Op_VecX, 60, NULL);
reg_def VSR61 ( SOC, SOC, Op_VecX, 61, NULL);
reg_def VSR62 ( SOC, SOC, Op_VecX, 62, NULL);
reg_def VSR63 ( SOC, SOC, Op_VecX, 63, NULL);
// ----------------------------
// Specify priority of register selection within phases of register
// allocation. Highest priority is first. A useful heuristic is to
// give registers a low priority when they are required by machine
// instructions, like EAX and EDX on I486, and choose no-save registers
// before save-on-call, & save-on-call before save-on-entry. Registers
// which participate in fixed calling sequences should come last.
// Registers which are used as pairs must fall on an even boundary.
// It's worth about 1% on SPEC geomean to get this right.
// Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
// in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
// R3_num. Therefore, R3_num may not be (and in reality is not)
// the same as R3->encoding()! Furthermore, we cannot make any
// assumptions on ordering, e.g. R3_num may be less than R2_num.
// Additionally, the function
// static enum RC rc_class(OptoReg::Name reg )
// maps a given <register>_num value to its chunk type (except for flags)
// and its current implementation relies on chunk0 and chunk1 having a
// size of 64 each.
// If you change this allocation class, please have a look at the
// default values for the parameters RoundRobinIntegerRegIntervalStart
// and RoundRobinFloatRegIntervalStart
alloc_class chunk0 (
// Chunk0 contains *all* 64 integer registers halves.
// "non-volatile" registers
R14, R14_H,
R15, R15_H,
R17, R17_H,
R18, R18_H,
R19, R19_H,
R20, R20_H,
R21, R21_H,
R22, R22_H,
R23, R23_H,
R24, R24_H,
R25, R25_H,
R26, R26_H,
R27, R27_H,
R28, R28_H,
R29, R29_H,
R30, R30_H,
R31, R31_H,
// scratch/special registers
R11, R11_H,
R12, R12_H,
// argument registers
R10, R10_H,
R9, R9_H,
R8, R8_H,
R7, R7_H,
R6, R6_H,
R5, R5_H,
R4, R4_H,
R3, R3_H,
// special registers, not available for allocation
R16, R16_H, // R16_thread
R13, R13_H, // system thread id
R2, R2_H, // may be used for TOC
R1, R1_H, // SP
R0, R0_H // R0 (scratch)
);
// If you change this allocation class, please have a look at the
// default values for the parameters RoundRobinIntegerRegIntervalStart
// and RoundRobinFloatRegIntervalStart
alloc_class chunk1 (
// Chunk1 contains *all* 64 floating-point registers halves.
// scratch register
F0, F0_H,
// argument registers
F13, F13_H,
F12, F12_H,
F11, F11_H,
F10, F10_H,
F9, F9_H,
F8, F8_H,
F7, F7_H,
F6, F6_H,
F5, F5_H,
F4, F4_H,
F3, F3_H,
F2, F2_H,
F1, F1_H,
// non-volatile registers
F14, F14_H,
F15, F15_H,
F16, F16_H,
F17, F17_H,
F18, F18_H,
F19, F19_H,
F20, F20_H,
F21, F21_H,
F22, F22_H,
F23, F23_H,
F24, F24_H,
F25, F25_H,
F26, F26_H,
F27, F27_H,
F28, F28_H,
F29, F29_H,
F30, F30_H,
F31, F31_H
);
alloc_class chunk2 (
// Chunk2 contains *all* 8 condition code registers.
CCR0,
CCR1,
CCR2,
CCR3,
CCR4,
CCR5,
CCR6,
CCR7
);
alloc_class chunk3 (
VSR0,
VSR1,
VSR2,
VSR3,
VSR4,
VSR5,
VSR6,
VSR7,
VSR8,
VSR9,
VSR10,
VSR11,
VSR12,
VSR13,
VSR14,
VSR15,
VSR16,
VSR17,
VSR18,
VSR19,
VSR20,
VSR21,
VSR22,
VSR23,
VSR24,
VSR25,
VSR26,
VSR27,
VSR28,
VSR29,
VSR30,
VSR31,
VSR32,
VSR33,
VSR34,
VSR35,
VSR36,
VSR37,
VSR38,
VSR39,
VSR40,
VSR41,
VSR42,
VSR43,
VSR44,
VSR45,
VSR46,
VSR47,
VSR48,
VSR49,
VSR50,
VSR51,
VSR52,
VSR53,
VSR54,
VSR55,
VSR56,
VSR57,
VSR58,
VSR59,
VSR60,
VSR61,
VSR62,
VSR63
);
alloc_class chunk4 (
// special registers
// These registers are not allocated, but used for nodes generated by postalloc expand.
SR_XER,
SR_LR,
SR_CTR,
SR_VRSAVE,
SR_SPEFSCR,
SR_PPR
);
//-------Architecture Description Register Classes-----------------------
// Several register classes are automatically defined based upon
// information in this architecture description.
// 1) reg_class inline_cache_reg ( as defined in frame section )
// 2) reg_class compiler_method_oop_reg ( as defined in frame section )
// 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
//
// ----------------------------
// 32 Bit Register Classes
// ----------------------------
// We specify registers twice, once as read/write, and once read-only.
// We use the read-only registers for source operands. With this, we
// can include preset read only registers in this class, as a hard-coded
// '0'-register. (We used to simulate this on ppc.)
// 32 bit registers that can be read and written i.e. these registers
// can be dest (or src) of normal instructions.
reg_class bits32_reg_rw(
/*R0*/ // R0
/*R1*/ // SP
R2, // TOC
R3,
R4,
R5,
R6,
R7,
R8,
R9,
R10,
R11,
R12,
/*R13*/ // system thread id
R14,
R15,
/*R16*/ // R16_thread
R17,
R18,
R19,
R20,
R21,
R22,
R23,
R24,
R25,
R26,
R27,
R28,
/*R29,*/ // global TOC
R30,
R31
);
// 32 bit registers that can only be read i.e. these registers can
// only be src of all instructions.
reg_class bits32_reg_ro(
/*R0*/ // R0
/*R1*/ // SP
R2 // TOC
R3,
R4,
R5,
R6,
R7,
R8,
R9,
R10,
R11,
R12,
/*R13*/ // system thread id
R14,
R15,
/*R16*/ // R16_thread
R17,
R18,
R19,
R20,
R21,
R22,
R23,
R24,
R25,
R26,
R27,
R28,
/*R29,*/
R30,
R31
);
reg_class rscratch1_bits32_reg(R11);
reg_class rscratch2_bits32_reg(R12);
reg_class rarg1_bits32_reg(R3);
reg_class rarg2_bits32_reg(R4);
reg_class rarg3_bits32_reg(R5);
reg_class rarg4_bits32_reg(R6);
// ----------------------------
// 64 Bit Register Classes
// ----------------------------
// 64-bit build means 64-bit pointers means hi/lo pairs
reg_class rscratch1_bits64_reg(R11_H, R11);
reg_class rscratch2_bits64_reg(R12_H, R12);
reg_class rarg1_bits64_reg(R3_H, R3);
reg_class rarg2_bits64_reg(R4_H, R4);
reg_class rarg3_bits64_reg(R5_H, R5);
reg_class rarg4_bits64_reg(R6_H, R6);
// Thread register, 'written' by tlsLoadP, see there.
reg_class thread_bits64_reg(R16_H, R16);
reg_class r19_bits64_reg(R19_H, R19);
// 64 bit registers that can be read and written i.e. these registers
// can be dest (or src) of normal instructions.
reg_class bits64_reg_rw(
/*R0_H, R0*/ // R0
/*R1_H, R1*/ // SP
R2_H, R2, // TOC
R3_H, R3,
R4_H, R4,
R5_H, R5,
R6_H, R6,
R7_H, R7,
R8_H, R8,
R9_H, R9,
R10_H, R10,
R11_H, R11,
R12_H, R12,
/*R13_H, R13*/ // system thread id
R14_H, R14,
R15_H, R15,
/*R16_H, R16*/ // R16_thread
R17_H, R17,
R18_H, R18,
R19_H, R19,
R20_H, R20,
R21_H, R21,
R22_H, R22,
R23_H, R23,
R24_H, R24,
R25_H, R25,
R26_H, R26,
R27_H, R27,
R28_H, R28,
/*R29_H, R29,*/
R30_H, R30,
R31_H, R31
);
// 64 bit registers used excluding r2, r11 and r12
// Used to hold the TOC to avoid collisions with expanded LeafCall which uses
// r2, r11 and r12 internally.
reg_class bits64_reg_leaf_call(
/*R0_H, R0*/ // R0
/*R1_H, R1*/ // SP
/*R2_H, R2*/ // TOC
R3_H, R3,
R4_H, R4,
R5_H, R5,
R6_H, R6,
R7_H, R7,
R8_H, R8,
R9_H, R9,
R10_H, R10,
/*R11_H, R11*/
/*R12_H, R12*/
/*R13_H, R13*/ // system thread id
R14_H, R14,
R15_H, R15,
/*R16_H, R16*/ // R16_thread
R17_H, R17,
R18_H, R18,
R19_H, R19,
R20_H, R20,
R21_H, R21,
R22_H, R22,
R23_H, R23,
R24_H, R24,
R25_H, R25,
R26_H, R26,
R27_H, R27,
R28_H, R28,
/*R29_H, R29,*/
R30_H, R30,
R31_H, R31
);
// Used to hold the TOC to avoid collisions with expanded DynamicCall
// which uses r19 as inline cache internally and expanded LeafCall which uses
// r2, r11 and r12 internally.
reg_class bits64_constant_table_base(
/*R0_H, R0*/ // R0
/*R1_H, R1*/ // SP
/*R2_H, R2*/ // TOC
R3_H, R3,
R4_H, R4,
R5_H, R5,
R6_H, R6,
R7_H, R7,
R8_H, R8,
R9_H, R9,
R10_H, R10,
/*R11_H, R11*/
/*R12_H, R12*/
/*R13_H, R13*/ // system thread id
R14_H, R14,
R15_H, R15,
/*R16_H, R16*/ // R16_thread
R17_H, R17,
R18_H, R18,
/*R19_H, R19*/
R20_H, R20,
R21_H, R21,
R22_H, R22,
R23_H, R23,
R24_H, R24,
R25_H, R25,
R26_H, R26,
R27_H, R27,
R28_H, R28,
/*R29_H, R29,*/
R30_H, R30,
R31_H, R31
);
// 64 bit registers that can only be read i.e. these registers can
// only be src of all instructions.
reg_class bits64_reg_ro(
/*R0_H, R0*/ // R0
R1_H, R1,
R2_H, R2, // TOC
R3_H, R3,
R4_H, R4,
R5_H, R5,
R6_H, R6,
R7_H, R7,
R8_H, R8,
R9_H, R9,
R10_H, R10,
R11_H, R11,
R12_H, R12,
/*R13_H, R13*/ // system thread id
R14_H, R14,
R15_H, R15,
R16_H, R16, // R16_thread
R17_H, R17,
R18_H, R18,
R19_H, R19,
R20_H, R20,
R21_H, R21,
R22_H, R22,
R23_H, R23,
R24_H, R24,
R25_H, R25,
R26_H, R26,
R27_H, R27,
R28_H, R28,
/*R29_H, R29,*/ // TODO: let allocator handle TOC!!
R30_H, R30,
R31_H, R31
);
// ----------------------------
// Special Class for Condition Code Flags Register
reg_class int_flags(
/*CCR0*/ // scratch
/*CCR1*/ // scratch
/*CCR2*/ // nv!
/*CCR3*/ // nv!
/*CCR4*/ // nv!
CCR5,
CCR6,
CCR7
);
reg_class int_flags_ro(
CCR0,
CCR1,
CCR2,
CCR3,
CCR4,
CCR5,
CCR6,
CCR7
);
reg_class int_flags_CR0(CCR0);
reg_class int_flags_CR1(CCR1);
reg_class int_flags_CR6(CCR6);
reg_class ctr_reg(SR_CTR);
// ----------------------------
// Float Register Classes
// ----------------------------
reg_class flt_reg(
F0,
F1,
F2,
F3,
F4,
F5,
F6,
F7,
F8,
F9,
F10,
F11,
F12,
F13,
F14, // nv!
F15, // nv!
F16, // nv!
F17, // nv!
F18, // nv!
F19, // nv!
F20, // nv!
F21, // nv!
F22, // nv!
F23, // nv!
F24, // nv!
F25, // nv!
F26, // nv!
F27, // nv!
F28, // nv!
F29, // nv!
F30, // nv!
F31 // nv!
);
// Double precision float registers have virtual `high halves' that
// are needed by the allocator.
reg_class dbl_reg(
F0, F0_H,
F1, F1_H,
F2, F2_H,
F3, F3_H,
F4, F4_H,
F5, F5_H,
F6, F6_H,
F7, F7_H,
F8, F8_H,
F9, F9_H,
F10, F10_H,
F11, F11_H,
F12, F12_H,
F13, F13_H,
F14, F14_H, // nv!
F15, F15_H, // nv!
F16, F16_H, // nv!
F17, F17_H, // nv!
F18, F18_H, // nv!
F19, F19_H, // nv!
F20, F20_H, // nv!
F21, F21_H, // nv!
F22, F22_H, // nv!
F23, F23_H, // nv!
F24, F24_H, // nv!
F25, F25_H, // nv!
F26, F26_H, // nv!
F27, F27_H, // nv!
F28, F28_H, // nv!
F29, F29_H, // nv!
F30, F30_H, // nv!
F31, F31_H // nv!
);
// ----------------------------
// Vector-Scalar Register Class
// ----------------------------
reg_class vs_reg(
// Attention: Only these ones are saved & restored at safepoint by RegisterSaver.
VSR32,
VSR33,
VSR34,
VSR35,
VSR36,
VSR37,
VSR38,
VSR39,
VSR40,
VSR41,
VSR42,
VSR43,
VSR44,
VSR45,
VSR46,
VSR47,
VSR48,
VSR49,
VSR50,
VSR51
// VSR52-VSR63 // nv!
);
%}
//----------DEFINITION BLOCK---------------------------------------------------
// Define name --> value mappings to inform the ADLC of an integer valued name
// Current support includes integer values in the range [0, 0x7FFFFFFF]
// Format:
// int_def <name> ( <int_value>, <expression>);
// Generated Code in ad_<arch>.hpp
// #define <name> (<expression>)
// // value == <int_value>
// Generated code in ad_<arch>.cpp adlc_verification()
// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
//
definitions %{
// The default cost (of an ALU instruction).
int_def DEFAULT_COST_LOW ( 30, 30);
int_def DEFAULT_COST ( 100, 100);
int_def HUGE_COST (1000000, 1000000);
// Memory refs
int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
// Branches are even more expensive.
int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
int_def CALL_COST ( 1300, DEFAULT_COST * 13);
%}
//----------SOURCE BLOCK-------------------------------------------------------
// This is a block of C++ code which provides values, functions, and
// definitions necessary in the rest of the architecture description.
source_hpp %{
// Header information of the source block.
// Method declarations/definitions which are used outside
// the ad-scope can conveniently be defined here.
//
// To keep related declarations/definitions/uses close together,
// we switch between source %{ }% and source_hpp %{ }% freely as needed.
#include "opto/convertnode.hpp"
// Returns true if Node n is followed by a MemBar node that
// will do an acquire. If so, this node must not do the acquire
// operation.
bool followed_by_acquire(const Node *n);
%}
source %{
// Should the Matcher clone shifts on addressing modes, expecting them
// to be subsumed into complex addressing expressions or compute them
// into registers?
bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
return clone_base_plus_offset_address(m, mstack, address_visited);
}
void Compile::reshape_address(AddPNode* addp) {
}
// Optimize load-acquire.
//
// Check if acquire is unnecessary due to following operation that does
// acquire anyways.
// Walk the pattern:
//