8278337: riscv: remove unnecessary ld/sd zr around calls

[kuaiwei]

It seems zr(x0) is used as stack alignment when saving/restoring registers around calls. But it's unnecessary to ld/st x0 from/to stack. We just need reserve a stack slot in case alignment is required. It passed tier1 tests with fastdebug in qemu.

---

Progress

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Issue

• JDK-8278337: riscv: remove unnecessary ld/sd zr around calls

Reviewers

• Fei Yang (@RealFYang - Reviewer)

Reviewing

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Checkout this PR locally:
$ git fetch https://git.openjdk.java.net/riscv-port pull/25/head:pull/25
$ git checkout pull/25

Update a local copy of the PR:
$ git checkout pull/25
$ git pull https://git.openjdk.java.net/riscv-port pull/25/head

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$ git pr checkout 25

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$ git pr show -t 25

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Download this PR as a diff file:
https://git.openjdk.java.net/riscv-port/pull/25.diff

[bridgekeeper]

👋 Welcome back kuaiwei! A progress list of the required criteria for merging this PR into riscv-port will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

[mlbridge]

Webrevs

• 02: Full - Incremental (c64168c4)
• 01: Full - Incremental (ddc32f4e)
• 00: Full (5f8767ca)

[RealFYang]

May I ask what kind of test is carried out for this change? Normally, testing result should also be added in PR description.

[kuaiwei]

Hi Felix, the patch passed tier1 test in qemu with fastdebug build.

[RealFYang]

Hi Felix, the patch passed tier1 test in qemu with fastdebug build.

Thank you. Could you please add this to the PR description?

[RealFYang]

Looks good.

[openjdk]

@kuaiwei This change now passes all automated pre-integration checks.

ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details.

After integration, the commit message for the final commit will be:

8278337: riscv: remove unnecessary ld/sd zr around calls

Reviewed-by: fyang

You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed.

At the time when this comment was updated there had been 92 new commits pushed to the riscv-port branch:

• 62c9bc7: 8278387: riscv: Implement UseHeavyMonitors consistently
• f3c980c: Merge branch 'master' into riscv-port
• 5dcdee4: 8262341: Refine identical code in AddI/LNode.
• b334d96: 8276964: Better indicate a snippet that could not be processed
• 30f0c64: 8277992: Add fast jdk_svc subtests to jdk:tier3
• 5266e7d: 8278379: Zero VM is broken due to UseRTMForStackLocks was not declared after JDK-8276901
• e7db581: 8277168: AArch64: Enable arraycopy partial inlining with SVE
• aa0aaf8: Merge branch 'master' into riscv-port
• fb6d611: 8278276: G1: Refine naming of G1GCParPhaseTimesTracker::_must_record
• d7ad546: 8276422: Add command-line option to disable finalization
• ... and 82 more: https://git.openjdk.java.net/riscv-port/compare/df45709c5649ab216ed604ea1304dd96d118ed86...riscv-port

As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details.

As you do not have Committer status in this project an existing Committer must agree to sponsor your change. Possible candidates are the reviewers of this PR (@RealFYang) but any other Committer may sponsor as well.

➡️ To flag this PR as ready for integration with the above commit message, type /integrate in a new comment. (Afterwards, your sponsor types /sponsor in a new comment to perform the integration).

[kuaiwei]

Looks good.

Thanks.

[kuaiwei]

/integrate

[openjdk]

@kuaiwei
Your change (at version c64168c) is now ready to be sponsored by a Committer.

[RealFYang]

/sponsor

[openjdk]

Going to push as commit 1a43775.
Since your change was applied there have been 92 commits pushed to the riscv-port branch:

• 62c9bc7: 8278387: riscv: Implement UseHeavyMonitors consistently
• f3c980c: Merge branch 'master' into riscv-port
• 5dcdee4: 8262341: Refine identical code in AddI/LNode.
• b334d96: 8276964: Better indicate a snippet that could not be processed
• 30f0c64: 8277992: Add fast jdk_svc subtests to jdk:tier3
• 5266e7d: 8278379: Zero VM is broken due to UseRTMForStackLocks was not declared after JDK-8276901
• e7db581: 8277168: AArch64: Enable arraycopy partial inlining with SVE
• aa0aaf8: Merge branch 'master' into riscv-port
• fb6d611: 8278276: G1: Refine naming of G1GCParPhaseTimesTracker::_must_record
• d7ad546: 8276422: Add command-line option to disable finalization
• ... and 82 more: https://git.openjdk.java.net/riscv-port/compare/df45709c5649ab216ed604ea1304dd96d118ed86...riscv-port

Your commit was automatically rebased without conflicts.

[openjdk]

@RealFYang @kuaiwei Pushed as commit 1a43775.

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