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Add support to
while
loops in OpenQASM3 frontend (#5)
This PR adds support to while loop in OpenQASM3 frontend. For a OpenQASM3 program: ```qasm OPENQASM 3.0; gate h q { U(1.57079632679, 0.0, 3.14159265359) q; } qubit $0; int n = 5; while (n > 0) { h $0; // error: Binary operation ASTOpTypeSub not supported yet. // n = n - 1; } ``` generates MLIR: ```mlir ... scf.while : () -> () { %2 = quir.use_variable @n : i32 %c0_i32_0 = arith.constant 0 : i32 %3 = arith.cmpi sgt, %2, %c0_i32_0 : i32 scf.condition(%3) } do { quir.call_gate @h(%0) : (!quir.qubit<1>) -> () %cst = constant unit scf.yield } } ... ```
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OPENQASM 3.0; | ||
// RUN: qss-compiler -X=qasm --emit=ast-pretty %s | FileCheck %s --match-full-lines --check-prefix AST-PRETTY | ||
// RUN: qss-compiler -X=qasm --emit=mlir %s | FileCheck %s --match-full-lines --check-prefix MLIR | ||
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gate h q { | ||
U(1.57079632679, 0.0, 3.14159265359) q; | ||
} | ||
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qubit $0; | ||
int n = 1; | ||
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bit is_excited; | ||
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// AST-PRETTY: WhileStatement(condition=BinaryOpNode(type=ASTOpTypeCompNeq, left=IdentifierNode(name=n, bits=32), right=IntNode(signed=true, value=0, bits=32)) | ||
// MLIR: scf.while : () -> () { | ||
// MLIR: %2 = quir.use_variable @n : i32 | ||
// MLIR: %c0_i32_0 = arith.constant 0 : i32 | ||
// MLIR: %3 = arith.cmpi ne, %2, %c0_i32_0 : i32 | ||
// MLIR: scf.condition(%3) | ||
// MLIR: } do { | ||
while (n != 0) { | ||
// AST-PRETTY: statements= | ||
// AST-PRETTY: HGateOpNode(params=[], qubits=[], qcparams=[$0]) | ||
// MLIR: quir.call_gate @h(%0) : (!quir.qubit<1>) -> () | ||
// MLIR: %cst = constant unit | ||
h $0; | ||
// MLIR: %2 = quir.measure(%0) : (!quir.qubit<1>) -> i1 | ||
// MLIR: quir.assign_cbit_bit @is_excited<1> [0] : i1 = %2 | ||
// MLIR: %3 = quir.use_variable @is_excited : !quir.cbit<1> | ||
// MLIR: %4 = "quir.cast"(%3) : (!quir.cbit<1>) -> i1 | ||
is_excited = measure $0; | ||
// MLIR: scf.if %4 { | ||
if (is_excited) { | ||
// MLIR: quir.call_gate @h(%0) : (!quir.qubit<1>) -> () | ||
// MLIR: %cst_1 = constant unit | ||
// MLIR: } | ||
h $0; | ||
} | ||
// error: Binary operation ASTOpTypeSub not supported yet. | ||
// n = n - 1; | ||
// MLIR: %c0_i32_0 = arith.constant 0 : i32 | ||
// MLIR: quir.assign_variable @n : i32 = %c0_i32_0 | ||
n = 0; // workaround for n = n - 1 | ||
// MLIR: scf.yield | ||
} | ||
// AST-PRETTY: ) |
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OPENQASM 3.0; | ||
// RUN: qss-compiler -X=qasm --emit=ast-pretty %s | FileCheck %s --match-full-lines --check-prefix AST-PRETTY | ||
// RUN: qss-compiler -X=qasm --emit=mlir %s | FileCheck %s --match-full-lines --check-prefix MLIR | ||
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gate h q { | ||
U(1.57079632679, 0.0, 3.14159265359) q; | ||
} | ||
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qubit $0; | ||
int n = 2; | ||
bit is_excited; | ||
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// AST-PRETTY: WhileStatement(condition=BinaryOpNode(type=ASTOpTypeCompNeq, left=IdentifierNode(name=n, bits=32), right=IntNode(signed=true, value=0, bits=32)) | ||
// MLIR: scf.while : () -> () { | ||
// MLIR: %2 = quir.use_variable @n : i32 | ||
// MLIR: %c0_i32_0 = arith.constant 0 : i32 | ||
// MLIR: %3 = arith.cmpi ne, %2, %c0_i32_0 : i32 | ||
// MLIR: scf.condition(%3) | ||
// MLIR: } do { | ||
while (n != 0) { | ||
// MLIR: %2 = quir.use_variable @n : i32 | ||
// MLIR: %c2_i32_0 = arith.constant 2 : i32 | ||
// MLIR: %3 = arith.cmpi eq, %2, %c2_i32_0 : i32 | ||
// MLIR: scf.if %3 { | ||
if (n == 2) { | ||
// MLIR: quir.call_gate @h(%0) : (!quir.qubit<1>) -> () | ||
// MLIR: %cst = constant unit | ||
// MLIR: %c1_i32 = arith.constant 1 : i32 | ||
// MLIR: quir.assign_variable @n : i32 = %c1_i32 | ||
h $0; | ||
n = 1; | ||
// MLIR: } else { | ||
} else { | ||
// MLIR: quir.call_gate @h(%0) : (!quir.qubit<1>) -> () | ||
// MLIR: %cst = constant unit | ||
// MLIR: %4 = quir.measure(%0) : (!quir.qubit<1>) -> i1 | ||
// MLIR: quir.assign_cbit_bit @is_excited<1> [0] : i1 = %4 | ||
// MLIR: %c0_i32_1 = arith.constant 0 : i32 | ||
// MLIR: quir.assign_variable @n : i32 = %c0_i32_1 | ||
h $0; | ||
is_excited = measure $0; | ||
n = 0; | ||
} | ||
// MLIR: scf.yield | ||
} | ||
// AST-PRETTY: ) |
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