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Merge pull request #13 from stffrdhrn/or1k-spec-1.3
Page updates for spec verison 1.3
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--- | ||
layout: post | ||
title: "Announcing Architecture Version 1.3" | ||
description: "" | ||
category: | ||
tags: [] | ||
author: Stafford Horne | ||
--- | ||
{% include JB/setup %} | ||
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It has been been a few years since the release of [OpenRISC version 1.2](/revisions/r1.2). | ||
But, it's been a busy few years of getting GDB and GCC ports upstream. Now with | ||
the GCC port upstream we are able to make progress and this new architecture | ||
revision does just that bringing in a handful of new instructions: | ||
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- New instruction `lf.stod.d` for converting floats from single precision to | ||
double prevision | ||
- New instruction `lf.dtos.d` for converting floats from double precision to | ||
single precision | ||
- New instruction `l.adrp` for constructing addresses | ||
- New instructions `lf.sfun*` to support unordered compares | ||
- New instruction `l.lf` to load floats with NaN boxing on 64-bit hardware | ||
- Remove instructions `lf.rem.d` and `lf.rem.s` used for calculating floating point remainder | ||
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Perhaps one of the biggest new features is the addition of support for | ||
performing double precision floating point operations using 32-bit hardware. | ||
The is by way of the new [ORFPX64A32](/proposals/orfpx64a32) | ||
instruction set extension. | ||
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With that said OpenRISC architecture specification | ||
[version 1.3](https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf) | ||
has been released. Quite a few of the instructions and changes are already | ||
implemented in OpenRISC soft cores and toolchains so you should be able to use | ||
them right away. | ||
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See the full details on the [release](/revisions/r1.3) page. | ||
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## Soft Core Support | ||
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Some soft cores already support the new instructions if you want to try them out | ||
you can find them here: | ||
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- [mor1kx](https://github.com/openrisc/mor1kx) - has support for `lf.sfun*` | ||
operations. | ||
- [or1k_marocchino](https://github.com/openrisc/or1k_marocchino) - has support | ||
for `lf.sfun*` operations as well as the `ORFPX64A32` extension. | ||
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## Software Upstreaming Effort | ||
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In order for the new features to be useful to most users they must be available | ||
in OpenRISC software. Stafford is working on submitting toolchain patches for | ||
the following components. | ||
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- [GCC](https://github.com/stffrdhrn/gcc/tree/or1k-fpu-2) - Patches, ready | ||
to go but depends on binutils being in first. | ||
- [binutils](https://github.com/stffrdhrn/binutils-gdb/tree/orfpx64a32-3) - Working | ||
on adding test cases for the `l.adrp` instruction. Should send for upstream | ||
review in a few weeks. | ||
- [cgen](https://github.com/stffrdhrn/cgen)- Added unordered support to | ||
support binutils, [patches submitted](https://sourceware.org/ml/cgen/2019-q2/msg00013.html) waiting for review. | ||
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Please feel free to contact us via the [mailing list](/community) if you have any questions. |
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--- | ||
layout: page | ||
title: Revision 1.0 | ||
title: Version 1.0 | ||
date: 2012-12-14 | ||
category: released | ||
tagline: | ||
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--- | ||
layout: page | ||
title: Revision 1.1 | ||
title: Version 1.1 | ||
date: 2014-05-12 | ||
category: released | ||
tagline: | ||
|
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--- | ||
layout: page | ||
title: Revision 1.2 | ||
title: Version 1.2 | ||
date: 2017-10-21 | ||
category: released | ||
tagline: | ||
|
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--- | ||
layout: page | ||
title: Version 1.3 | ||
date: 2019-06-04 | ||
category: released | ||
tagline: | ||
--- | ||
{% include JB/setup %} | ||
- **Download** [pdf](https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf) | ||
- **Changes** | ||
- ORFPX64A32 double-precision floating point operations on 32-bit hardware using register pairs (P14) | ||
- Define `CPUCFGR[15]` for ORFPX64A32 presence flag | ||
- New instructions `lf.stod.d` `lf.dtos.d` for converting between single and double precision floats (P7) | ||
- New instruction `l.adrp` for constructing addresses (P9) | ||
- New instructions `lf.sfun*` to support unordered compares (P11) | ||
- New instruction `l.lf` to load floats with NaN boxing on 64-bit hardware | ||
- Removed instructions `lf.rem.d` and `lf.rem.s` used to calculate floating point remainder | ||
- Various cleanups and clarifications on internal rounding, truncation and others | ||
- Clarification on internal rounding for `lf.madd.*` instructions (P6) | ||
- Update `l.div*` to mention fraction is truncated | ||
- Update `lf.ftoi.*` to mention fraction is truncated (P13) | ||
- Add single-precision floating point NaN boxing on 64-bit hardware | ||
- Updated machine instruction table (Section 18), removed unused page column, added class and opcode for quick reference | ||
- Document `lf.sf*` floating point exceptions | ||
- Document that floating point exceptions do write back results to registers | ||
- Define addresses for `FPMADD*` and `VMAC*` sprs | ||
- **Authors** Stafford Horne <shorne@gmail.com>, Andrey Bacherov <bandvig@mail.ru> | ||
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<!--more--> | ||
## Details of Additions/Changes | ||
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{% for proposal in site.proposals %} | ||
{% if proposal.category == "r1.3" %} | ||
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### [{{ proposal.title }}]({{proposal.url}}) | ||
*{{proposal.date | date: "%Y-%m-%d"}} - {{proposal.author}}* | ||
{{proposal.excerpt}} | ||
--- | ||
{% endif %} | ||
{% endfor %} | ||
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