Make FPCSR is R/W accessible for both user- and supervisor- modes.

openrisc · Jan 15, 2022 · cd9e2bd · cd9e2bd
1 parent 79ce290
commit cd9e2bd
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/rtl/verilog/or1k_marocchino_ctrl.v b/rtl/verilog/or1k_marocchino_ctrl.v
@@ -714,7 +714,7 @@ module or1k_marocchino_ctrl
   assign except_fpu_enable_o = spr_fpcsr[`OR1K_FPCSR_FPEE];
 
   wire spr_fpcsr_we = (`SPR_OFFSET(({1'b0, spr_sys_group_wadr_r})) == `SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR)) &
-                      spr_sys_group_we &  spr_sr[`OR1K_SPR_SR_SM];
+                      spr_sys_group_we; // FPCSR is R/W for both user- and supervisor- modes
 
  `ifdef OR1K_FPCSR_MASK_FLAGS
   reg [`OR1K_FPCSR_ALLF_SIZE-1:0] ctrl_fpu_mask_flags_r;