Fixes proposed by Athanasios Moschos (https://github.com/0ena). (1) A…

…dd "or1k_defines.v" include into or1k_marocchino_monitor.v (2) Move qm_r declaration before 1st usage in pfpu_marocchino_div.v. Both the issues cause error in Modelsim.
openrisc · Jul 27, 2020 · d63dbac · d63dbac
1 parent 8be054f
commit d63dbac
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/bench/verilog/or1k_marocchino_monitor.v b/bench/verilog/or1k_marocchino_monitor.v
@@ -22,6 +22,8 @@
 //                                                                    //
 ////////////////////////////////////////////////////////////////////////
 
+`include "or1k_defines.v"
+
 /* Configure these defines to point to the marocchino instantiation */
 `ifndef OR1K_INST
  `define OR1K_INST dut.gencpu.or1k_marocchino0

diff --git a/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v b/rtl/verilog/pfpu_marocchino/pfpu_marocchino_div.v
@@ -187,6 +187,8 @@ module r4div_fract58
   // signed digits to tow's complement on the fly converter
   //  # part Q
   reg   [N-1:0] q_r;
+  //  # part QM
+  reg   [N-1:0] qm_r;
   //  # ---
   always @(posedge cpu_clk) begin
     if (div_start_i)
@@ -204,8 +206,6 @@ module r4div_fract58
       endcase
     end
   end // @clock
-  //  # part QM
-  reg   [N-1:0] qm_r;
   //  # ---
   always @(posedge cpu_clk) begin
     if (div_start_i)