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64 changes: 64 additions & 0 deletions
64
src/plugins/intel_cpu/src/nodes/executors/acl/acl_executor.cpp
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| @@ -0,0 +1,64 @@ | ||
| // Copyright (C) 2024 Intel Corporation | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
| // | ||
|
|
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| #include "acl_executor.hpp" | ||
| #include "acl_utils.hpp" | ||
| #include "nodes/executors/executor.hpp" | ||
| #include "nodes/executors/memory_arguments.hpp" | ||
| #include "utils/debug_capabilities.h" | ||
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| namespace ov { | ||
| namespace intel_cpu { | ||
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| bool ACLCommonExecutor::update(const MemoryArgs &memory) { | ||
| std::unordered_map<int, arm_compute::DataType> acl_tensors_types_list; | ||
| std::unordered_map<int, arm_compute::DataLayout> acl_tensors_layouts_list; | ||
| for (auto& cpu_mem_ptr : memory) { | ||
| acl_tensors_types_list[cpu_mem_ptr.first] = precisionToAclDataType(cpu_mem_ptr.second->getPrecision()); | ||
| acl_tensors_layouts_list[cpu_mem_ptr.first] = getAclDataLayoutByMemoryDesc(cpu_mem_ptr.second->getDescPtr()); | ||
| } | ||
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| for (auto& cpu_mem_ptr : memory) { | ||
| if (acl_tensors_types_list[cpu_mem_ptr.first] == arm_compute::DataType::UNKNOWN) { | ||
| list_acl_tensors_infos[cpu_mem_ptr.first] = arm_compute::TensorInfo(); | ||
| continue; | ||
| } | ||
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| auto collapsed_dims = collapse_dims_to_max_rank(cpu_mem_ptr.second->getStaticDims(), | ||
| aclTensorAttrs.maxDimsShape); | ||
| auto acl_tensor_shape = shapeCast(collapsed_dims); | ||
| if (aclTensorAttrs.enableNHWCReshape) { | ||
| changeLayoutToNH_C({&acl_tensor_shape}); | ||
| } | ||
| list_acl_tensors_infos[cpu_mem_ptr.first] = arm_compute::TensorInfo(acl_tensor_shape, 1, | ||
| acl_tensors_types_list[cpu_mem_ptr.first], | ||
| acl_tensors_layouts_list[cpu_mem_ptr.first]); | ||
| } | ||
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| auto status = prepare_tensors_info(); | ||
| if (!status) { | ||
| DEBUG_LOG("ACL operator validation was failed: ", status.error_description()); | ||
| return false; | ||
| } | ||
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| for (auto& acl_tensor_info : list_acl_tensors_infos) { | ||
| list_acl_tensors[acl_tensor_info.first].allocator()->init(acl_tensor_info.second); | ||
| } | ||
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| configureThreadSafe([&] { ifunc = configure_function();}); | ||
| return true; | ||
| } | ||
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| void ACLCommonExecutor::execute(const MemoryArgs &memory) { | ||
| for (auto& acl_tensor : list_acl_tensors) { | ||
| acl_tensor.second.allocator()->import_memory(memory.at(acl_tensor.first)->getData()); | ||
| } | ||
| ifunc->run(); | ||
| for (auto& acl_tensor : list_acl_tensors) { | ||
| acl_tensor.second.allocator()->free(); | ||
| } | ||
| } | ||
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| } // namespace intel_cpu | ||
| } // namespace ov |
38 changes: 38 additions & 0 deletions
38
src/plugins/intel_cpu/src/nodes/executors/acl/acl_executor.hpp
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| @@ -0,0 +1,38 @@ | ||
| // Copyright (C) 2018-2024 Intel Corporation | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
| // | ||
|
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| #pragma once | ||
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| #include "cpu_memory.h" | ||
| #include "nodes/executors/executor.hpp" | ||
| #include "arm_compute/runtime/NEON/NEFunctions.h" | ||
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| namespace ov { | ||
| namespace intel_cpu { | ||
|
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| struct ACLTensorAttrs { | ||
| bool enableNHWCReshape = false; | ||
| size_t maxDimsShape = arm_compute::MAX_DIMS; | ||
| }; | ||
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| class ACLCommonExecutor : public Executor { | ||
| public: | ||
| virtual arm_compute::Status prepare_tensors_info() = 0; | ||
| virtual std::unique_ptr<arm_compute::IFunction> configure_function() = 0; | ||
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| protected: | ||
| std::unique_ptr<arm_compute::IFunction> ifunc = nullptr; | ||
| std::unordered_map<int, arm_compute::Tensor> list_acl_tensors; | ||
| std::unordered_map<int, arm_compute::TensorInfo> list_acl_tensors_infos; | ||
| ACLTensorAttrs aclTensorAttrs; | ||
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| private: | ||
| void execute(const MemoryArgs& memory) override; | ||
| bool update(const MemoryArgs& memory) override; | ||
| }; | ||
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| using ACLCommonExecutorPtr = std::shared_ptr<ACLCommonExecutor>; | ||
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| } // namespace intel_cpu | ||
| } // namespace ov |
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114
src/plugins/intel_cpu/src/nodes/executors/acl/acl_fullyconnected.cpp
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,114 @@ | ||
| // Copyright (C) 2024 Intel Corporation | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
| // | ||
|
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| #include "acl_fullyconnected.hpp" | ||
| #include "acl_utils.hpp" | ||
| #include "nodes/executors/executor.hpp" | ||
| #include "nodes/executors/memory_arguments.hpp" | ||
| #include "utils/debug_capabilities.h" | ||
|
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| namespace ov { | ||
| namespace intel_cpu { | ||
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| ACLFullyConnectedExecutor::ACLFullyConnectedExecutor(const FCAttrs &attrs, const PostOps &postOps, | ||
| const MemoryArgs &memory, | ||
| const ExecutorContext::CPtr context) : withBias(attrs.withBias) { | ||
| aclTensorAttrs.enableNHWCReshape = memory.at(ARG_SRC)->getDescPtr()->hasLayoutType(LayoutType::nspc); | ||
| fullyConnectedLayerInfo.weights_trained_layout = getAclDataLayoutByMemoryDesc(memory.at(ARG_WEI)->getDescPtr()); | ||
| fullyConnectedLayerInfo.transpose_weights = !attrs.weightsNonTransposed; | ||
| if (memory.at(ARG_SRC)->getPrecision() == ov::element::f16) { | ||
| fullyConnectedLayerInfo.fp_mixed_precision = true; | ||
| } | ||
|
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| // Add postops | ||
| if (!postOps.empty() && postOps.size() == 1) { | ||
| if (const auto activation = std::dynamic_pointer_cast<ActivationPostOp>(postOps[0])) { | ||
| fullyConnectedLayerInfo.activation_info = getActivationLayerInfo(convertToEltwiseAlgorithm(activation->type()), | ||
| activation->alpha(), | ||
| activation->beta(), | ||
| activation->gamma()); | ||
| } | ||
| } | ||
| } | ||
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| bool ACLFullyConnectedExecutor::supports(const FCConfig &config) { | ||
| if (!config.postOps.empty() && config.postOps.size() != 1) { | ||
| DEBUG_LOG("ACLFullyConnectedExecutor supports only 1 post op"); | ||
| return false; | ||
| } | ||
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| const auto& srcDesc = config.descs.at(ARG_SRC); | ||
| if (!one_of(srcDesc->getShape().getDims().size(), 2, 3, 4)) { | ||
| DEBUG_LOG("ACLFullyConnectedExecutor supports only 2, 3 or 4 dimensions for inputs"); | ||
| return false; | ||
| } | ||
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| const auto& weiDesc = config.descs.at(ARG_WEI); | ||
| if (!one_of(weiDesc->getShape().getDims().size(), 2, 3)) { | ||
| DEBUG_LOG("ACLFullyConnectedExecutor supports only 2 or 3 dimensions for weights"); | ||
| return false; | ||
| } | ||
| return true; | ||
| } | ||
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| arm_compute::Status ACLFullyConnectedExecutor::prepare_tensors_info() { | ||
| auto wei_shape = list_acl_tensors_infos.at(ARG_WEI).tensor_shape(); | ||
| if (wei_shape.num_dimensions() == 3) { | ||
| list_acl_tensors_infos.at(ARG_WEI).set_tensor_shape({wei_shape[0], wei_shape[1] * wei_shape[2]}); | ||
| wei_shape = list_acl_tensors_infos.at(ARG_WEI).tensor_shape(); | ||
| } | ||
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| auto src_shape = list_acl_tensors_infos.at(ARG_SRC).tensor_shape(); | ||
| if (one_of(src_shape.num_dimensions(), 3, 4)) { | ||
| list_acl_tensors_infos.at(ARG_SRC).set_tensor_shape({wei_shape[0], src_shape.total_size() / wei_shape[0]}); | ||
| src_shape = list_acl_tensors_infos.at(ARG_SRC).tensor_shape(); | ||
| } | ||
|
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| if (one_of(list_acl_tensors_infos.at(ARG_DST).tensor_shape().num_dimensions(), 3, 4)) { | ||
| list_acl_tensors_infos.at(ARG_DST).set_tensor_shape({wei_shape[1], src_shape[1]}); | ||
| } | ||
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| auto expected_weight_format = arm_compute::WeightFormat::ANY; | ||
| weightsInfo = arm_compute::WeightsInfo(false, 1, 1, | ||
| list_acl_tensors_infos.at(ARG_WEI).tensor_shape().total_size(), | ||
| false, expected_weight_format); | ||
|
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| auto opt_impl_status = arm_compute::NEFullyConnectedLayer::has_opt_impl( | ||
| expected_weight_format, | ||
| &list_acl_tensors_infos.at(ARG_SRC), | ||
| &list_acl_tensors_infos.at(ARG_WEI), | ||
| withBias ? &list_acl_tensors_infos.at(ARG_BIAS) : nullptr, | ||
| &list_acl_tensors_infos.at(ARG_DST), | ||
| fullyConnectedLayerInfo, | ||
| weightsInfo); | ||
| if (!opt_impl_status) { return opt_impl_status; } | ||
| fullyConnectedLayerInfo.enable_fast_math = arm_compute::is_fixed_format_fast_math(expected_weight_format); | ||
|
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| if (!fullyConnectedLayerInfo.transpose_weights) { | ||
| arm_compute::TensorShape temp_weights_shape = list_acl_tensors_infos.at(ARG_WEI).tensor_shape(); | ||
| std::swap(temp_weights_shape[0], temp_weights_shape[1]); | ||
| list_acl_tensors_infos.at(ARG_WEI).set_tensor_shape(temp_weights_shape); | ||
| } | ||
|
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| return arm_compute::NEFullyConnectedLayer::validate(&list_acl_tensors_infos.at(ARG_SRC), | ||
| &list_acl_tensors_infos.at(ARG_WEI), | ||
| withBias ? &list_acl_tensors_infos.at(ARG_BIAS) : nullptr, | ||
| &list_acl_tensors_infos.at(ARG_DST), | ||
| fullyConnectedLayerInfo, | ||
| weightsInfo); | ||
| } | ||
|
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| std::unique_ptr<arm_compute::IFunction> ACLFullyConnectedExecutor::configure_function() { | ||
| auto fc_func = make_unique<arm_compute::NEFullyConnectedLayer>(); | ||
| fc_func->configure(&list_acl_tensors.at(ARG_SRC), | ||
| &list_acl_tensors.at(ARG_WEI), | ||
| withBias ? &list_acl_tensors.at(ARG_BIAS) : nullptr, | ||
| &list_acl_tensors.at(ARG_DST), | ||
| fullyConnectedLayerInfo, | ||
| weightsInfo); | ||
| return fc_func; | ||
| } | ||
|
|
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| } // namespace intel_cpu | ||
| } // namespace ov |
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