dpif-netdev-perf: Fix millisecond stats precision with slower TSC.

Unlike x86 where TSC frequency usually matches with CPU frequency,
another architectures could have much slower TSCs.
For example, it's common for Arm SoCs to have 100 MHz TSC by default.
In this case perf module will check for end of current millisecond
each 10K cycles, i.e 10 times per millisecond. This could be not
enough to collect precise statistics.
Fix that by taking current TSC frequency into account instead of
hardcoding the number of cycles.

CC: Jan Scheurich <jan.scheurich@ericsson.com>
Fixes: 79f3687 ("dpif-netdev: Detailed performance stats for PMDs")
Signed-off-by: Ilya Maximets <i.maximets@samsung.com>
Acked-by: Jan Scheurich <jan.scheurich@ericsson.com>
Signed-off-by: Ian Stokes <ian.stokes@intel.com>

lib/dpif-netdev-perf.c

@@ -554,8 +554,8 @@ pmd_perf_end_iteration(struct pmd_perf_stats *s, int rx_packets,
             cum_ms = history_next(&s->milliseconds);
             cum_ms->timestamp = now;
         }
-        /* Do the next check after 10K cycles (4 us at 2.5 GHz TSC clock). */
-        s->next_check_tsc = cycles_counter_update(s) + 10000;
+        /* Do the next check after 4 us (10K cycles at 2.5 GHz TSC clock). */
+        s->next_check_tsc = cycles_counter_update(s) + get_tsc_hz() / 250000;
     }
 }