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use the new bitfield accessor macros
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@nbd168
nbd168 committed Sep 4, 2016
1 parent 53c1b7f commit b300bdc
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Showing 17 changed files with 183 additions and 241 deletions.
10 changes: 5 additions & 5 deletions dma.c
View file
Expand Up @@ -66,10 +66,10 @@ mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
for (i = 0; i < nbufs; i += 2, buf += 2) {
u32 buf0 = buf[0].addr, buf1 = 0;

ctrl = MT76_SET(MT_DMA_CTL_SD_LEN0, buf[0].len);
ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
if (i < nbufs - 1) {
buf1 = buf[1].addr;
ctrl |= MT76_SET(MT_DMA_CTL_SD_LEN1, buf[1].len);
ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
}

if (i == nbufs - 1)
Expand Down Expand Up @@ -106,14 +106,14 @@ mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,

if (!e->txwi || !e->skb) {
__le32 addr = ACCESS_ONCE(q->desc[idx].buf0);
u32 len = MT76_GET(MT_DMA_CTL_SD_LEN0, ctrl);
u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl);
dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
DMA_TO_DEVICE);
}

if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) {
__le32 addr = ACCESS_ONCE(q->desc[idx].buf1);
u32 len = MT76_GET(MT_DMA_CTL_SD_LEN1, ctrl);
u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl);
dma_unmap_single(dev->dev, le32_to_cpu(addr), len,
DMA_TO_DEVICE);
}
Expand Down Expand Up @@ -194,7 +194,7 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
buf_addr = ACCESS_ONCE(desc->buf0);
if (len) {
u32 ctl = ACCESS_ONCE(desc->ctrl);
*len = MT76_GET(MT_DMA_CTL_SD_LEN0, ctl);
*len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
*more = !(ctl & MT_DMA_CTL_LAST_SEC0);
}

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4 changes: 2 additions & 2 deletions mt76.h
View file
Expand Up @@ -251,10 +251,10 @@ struct mt76_rate_power {
#define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)

#define mt76_get_field(_dev, _reg, _field) \
MT76_GET(_field, mt76_rr(dev, _reg))
FIELD_GET(_field, mt76_rr(dev, _reg))

#define mt76_rmw_field(_dev, _reg, _field, _val) \
mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))
mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))

#define mt76_hw(dev) (dev)->mt76.hw

Expand Down
2 changes: 1 addition & 1 deletion mt7603_beacon.c
View file
Expand Up @@ -158,7 +158,7 @@ void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval)

dev->beacon_int = intval;
mt76_wr(dev, MT_TBTT,
MT76_SET(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);
FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);

mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */

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2 changes: 1 addition & 1 deletion mt7603_dma.c
View file
Expand Up @@ -68,7 +68,7 @@ void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
__le32 *end = (__le32 *) &skb->data[skb->len];
enum rx_pkt_type type;

type = MT76_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));

switch(type) {
case PKT_TYPE_TXS:
Expand Down
2 changes: 1 addition & 1 deletion mt7603_eeprom.c
View file
Expand Up @@ -26,7 +26,7 @@ mt7603_efuse_read(struct mt7603_dev *dev, u32 base, u16 addr, u8 *data)
val = mt76_rr(dev, base + MT_EFUSE_CTRL);
val &= ~(MT_EFUSE_CTRL_AIN |
MT_EFUSE_CTRL_MODE);
val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf);
val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf);
val |= MT_EFUSE_CTRL_KICK;
mt76_wr(dev, base + MT_EFUSE_CTRL, val);

Expand Down
56 changes: 28 additions & 28 deletions mt7603_init.c
View file
Expand Up @@ -47,7 +47,7 @@ static void
mt7603_set_tmac_template(struct mt7603_dev *dev)
{
u32 desc[5] = {
[1] = MT76_SET(MT_TXD3_REM_TX_COUNT, 0xf),
[1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),
[3] = MT_TXD5_SW_POWER_MGMT
};
u32 addr;
Expand Down Expand Up @@ -79,9 +79,9 @@ mt7603_dma_sched_init(struct mt7603_dev *dev)
mcu_pages = max_mcu_len / page_size;

mt76_wr(dev, MT_PSE_FRP,
MT76_SET(MT_PSE_FRP_P0, 7) |
MT76_SET(MT_PSE_FRP_P1, 6) |
MT76_SET(MT_PSE_FRP_P2_RQ2, 4));
FIELD_PREP(MT_PSE_FRP_P0, 7) |
FIELD_PREP(MT_PSE_FRP_P1, 6) |
FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4));

mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
Expand Down Expand Up @@ -134,8 +134,8 @@ mt7603_phy_init(struct mt7603_dev *dev)
mt76_rmw(dev, MT_WF_RMAC_RMCR,
(MT_WF_RMAC_RMCR_SMPS_MODE |
MT_WF_RMAC_RMCR_RX_STREAMS),
(MT76_SET(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
MT76_SET(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
(FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));

mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
tx_chains);
Expand All @@ -161,25 +161,25 @@ mt7603_mac_init(struct mt7603_dev *dev)
(MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));

mt76_wr(dev, MT_AGG_LIMIT,
MT76_SET(MT_AGG_LIMIT_AC(0), 21) |
MT76_SET(MT_AGG_LIMIT_AC(1), 21) |
MT76_SET(MT_AGG_LIMIT_AC(2), 21) |
MT76_SET(MT_AGG_LIMIT_AC(3), 21));
FIELD_PREP(MT_AGG_LIMIT_AC(0), 21) |
FIELD_PREP(MT_AGG_LIMIT_AC(1), 21) |
FIELD_PREP(MT_AGG_LIMIT_AC(2), 21) |
FIELD_PREP(MT_AGG_LIMIT_AC(3), 21));

mt76_wr(dev, MT_AGG_LIMIT_1,
MT76_SET(MT_AGG_LIMIT_AC(0), 21) |
MT76_SET(MT_AGG_LIMIT_AC(1), 21) |
MT76_SET(MT_AGG_LIMIT_AC(2), 21) |
MT76_SET(MT_AGG_LIMIT_AC(3), 21));
FIELD_PREP(MT_AGG_LIMIT_AC(0), 21) |
FIELD_PREP(MT_AGG_LIMIT_AC(1), 21) |
FIELD_PREP(MT_AGG_LIMIT_AC(2), 21) |
FIELD_PREP(MT_AGG_LIMIT_AC(3), 21));

mt76_wr(dev, MT_AGG_CONTROL,
MT76_SET(MT_AGG_CONTROL_BAR_RATE, 0x80) |
MT76_SET(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x80) |
FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
MT_AGG_CONTROL_NO_BA_AR_RULE);

mt76_wr(dev, MT_AGG_RETRY_CONTROL,
MT76_SET(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
MT76_SET(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));

mt76_rmw(dev, MT_DMA_DCR0, ~0xfffc, MT_RX_BUF_SIZE);

Expand Down Expand Up @@ -213,7 +213,7 @@ mt7603_mac_init(struct mt7603_dev *dev)

/* Configure txs selection with aggregation */
mt76_wr(dev, MT_DMA_TCFR1,
MT76_SET(MT_DMA_TCFR1_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
FIELD_PREP(MT_DMA_TCFR1_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
MT_DMA_TCFR1_TXS_AGGR_COUNT | /* Maximum count */
MT_DMA_TCFR1_TXS_QUEUE | /* Queue 1 */
MT_DMA_TCFR1_TXS_BIT_MAP);
Expand All @@ -234,17 +234,17 @@ mt7603_mac_init(struct mt7603_dev *dev)

mt76_wr(dev, MT_AGG_ARUCR, 0);
mt76_wr(dev, MT_AGG_ARDCR,
MT76_SET(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
MT76_SET(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));

mt76_wr(dev, MT_AGG_ARCR, (MT_AGG_ARCR_INIT_RATE1 |
MT76_SET(MT_AGG_ARCR_RTS_RATE_THR, 2)));
FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2)));

mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE);

Expand Down

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